comm.hh revision 2980:eab855f06b79 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_COMM_HH__
32#define __CPU_O3_COMM_HH__
33
34#include <vector>
35
36#include "sim/faults.hh"
37#include "cpu/inst_seq.hh"
38#include "sim/host.hh"
39
40// Typedef for physical register index type. Although the Impl would be the
41// most likely location for this, there are a few classes that need this
42// typedef yet are not templated on the Impl. For now it will be defined here.
43typedef short int PhysRegIndex;
44
45/** Struct that defines the information passed from fetch to decode. */
46template<class Impl>
47struct DefaultFetchDefaultDecode {
48    typedef typename Impl::DynInstPtr DynInstPtr;
49
50    int size;
51
52    DynInstPtr insts[Impl::MaxWidth];
53    Fault fetchFault;
54    InstSeqNum fetchFaultSN;
55    bool clearFetchFault;
56};
57
58/** Struct that defines the information passed from decode to rename. */
59template<class Impl>
60struct DefaultDecodeDefaultRename {
61    typedef typename Impl::DynInstPtr DynInstPtr;
62
63    int size;
64
65    DynInstPtr insts[Impl::MaxWidth];
66};
67
68/** Struct that defines the information passed from rename to IEW. */
69template<class Impl>
70struct DefaultRenameDefaultIEW {
71    typedef typename Impl::DynInstPtr DynInstPtr;
72
73    int size;
74
75    DynInstPtr insts[Impl::MaxWidth];
76};
77
78/** Struct that defines the information passed from IEW to commit. */
79template<class Impl>
80struct DefaultIEWDefaultCommit {
81    typedef typename Impl::DynInstPtr DynInstPtr;
82
83    int size;
84
85    DynInstPtr insts[Impl::MaxWidth];
86
87    bool squash[Impl::MaxThreads];
88    bool branchMispredict[Impl::MaxThreads];
89    bool branchTaken[Impl::MaxThreads];
90    bool condDelaySlotBranch[Impl::MaxThreads];
91    uint64_t mispredPC[Impl::MaxThreads];
92    uint64_t nextPC[Impl::MaxThreads];
93    InstSeqNum squashedSeqNum[Impl::MaxThreads];
94
95    bool includeSquashInst[Impl::MaxThreads];
96};
97
98template<class Impl>
99struct IssueStruct {
100    typedef typename Impl::DynInstPtr DynInstPtr;
101
102    int size;
103
104    DynInstPtr insts[Impl::MaxWidth];
105};
106
107/** Struct that defines all backwards communication. */
108template<class Impl>
109struct TimeBufStruct {
110    struct decodeComm {
111        bool squash;
112        bool predIncorrect;
113        uint64_t branchAddr;
114
115        InstSeqNum doneSeqNum;
116        InstSeqNum bdelayDoneSeqNum;
117
118        // @todo: Might want to package this kind of branch stuff into a single
119        // struct as it is used pretty frequently.
120        bool branchMispredict;
121        bool branchTaken;
122        uint64_t mispredPC;
123        uint64_t nextPC;
124
125        unsigned branchCount;
126    };
127
128    decodeComm decodeInfo[Impl::MaxThreads];
129
130    struct renameComm {
131    };
132
133    renameComm renameInfo[Impl::MaxThreads];
134
135    struct iewComm {
136        // Also eventually include skid buffer space.
137        bool usedIQ;
138        unsigned freeIQEntries;
139        bool usedLSQ;
140        unsigned freeLSQEntries;
141
142        unsigned iqCount;
143        unsigned ldstqCount;
144
145        unsigned dispatched;
146        unsigned dispatchedToLSQ;
147    };
148
149    iewComm iewInfo[Impl::MaxThreads];
150
151    struct commitComm {
152        bool usedROB;
153        unsigned freeROBEntries;
154        bool emptyROB;
155
156        bool squash;
157        bool robSquashing;
158
159        bool branchMispredict;
160        bool branchTaken;
161        uint64_t mispredPC;
162        uint64_t nextPC;
163
164        // Represents the instruction that has either been retired or
165        // squashed.  Similar to having a single bus that broadcasts the
166        // retired or squashed sequence number.
167        InstSeqNum doneSeqNum;
168
169        InstSeqNum bdelayDoneSeqNum;
170        bool squashDelaySlot;
171
172        //Just in case we want to do a commit/squash on a cycle
173        //(necessary for multiple ROBs?)
174        bool commitInsts;
175        InstSeqNum squashSeqNum;
176
177        // Communication specifically to the IQ to tell the IQ that it can
178        // schedule a non-speculative instruction.
179        InstSeqNum nonSpecSeqNum;
180
181        // Hack for now to send back an uncached access to the IEW stage.
182        typedef typename Impl::DynInstPtr DynInstPtr;
183        bool uncached;
184        DynInstPtr uncachedLoad;
185
186        bool interruptPending;
187        bool clearInterrupt;
188    };
189
190    commitComm commitInfo[Impl::MaxThreads];
191
192    bool decodeBlock[Impl::MaxThreads];
193    bool decodeUnblock[Impl::MaxThreads];
194    bool renameBlock[Impl::MaxThreads];
195    bool renameUnblock[Impl::MaxThreads];
196    bool iewBlock[Impl::MaxThreads];
197    bool iewUnblock[Impl::MaxThreads];
198    bool commitBlock[Impl::MaxThreads];
199    bool commitUnblock[Impl::MaxThreads];
200};
201
202#endif //__CPU_O3_COMM_HH__
203