comm.hh revision 12109:f29e9c5418aa 
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Nathanael Premillieu
43 */
44
45#ifndef __CPU_O3_COMM_HH__
46#define __CPU_O3_COMM_HH__
47
48#include <vector>
49
50#include "arch/types.hh"
51#include "base/types.hh"
52#include "cpu/inst_seq.hh"
53#include "sim/faults.hh"
54
55/** Physical register index type.
56 * Although the Impl might be a better for this, but there are a few classes
57 * that need this typedef yet are not templated on the Impl.
58 */
59using PhysRegIndex = short int;
60
61/** Physical register ID.
62 * Like a register ID but physical. The inheritance is private because the
63 * only relationship between this types is functional, and it is done to
64 * prevent code replication. */
65class PhysRegId : private RegId {
66  private:
67    PhysRegIndex flatIdx;
68
69  public:
70    explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {}
71
72    /** Scalar PhysRegId constructor. */
73    explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
74              PhysRegIndex _flatIdx)
75        : RegId(_regClass, _regIdx), flatIdx(_flatIdx)
76    {}
77
78    /** Vector PhysRegId constructor (w/ elemIndex). */
79    explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
80              ElemIndex elem_idx, PhysRegIndex flat_idx)
81        : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx) { }
82
83    /** Visible RegId methods */
84    /** @{ */
85    using RegId::index;
86    using RegId::classValue;
87    using RegId::isZeroReg;
88    using RegId::className;
89    using RegId::elemIndex;
90     /** @} */
91    /**
92     * Explicit forward methods, to prevent comparisons of PhysRegId with
93     * RegIds.
94     */
95    /** @{ */
96    bool operator<(const PhysRegId& that) const {
97        return RegId::operator<(that);
98    }
99
100    bool operator==(const PhysRegId& that) const {
101        return RegId::operator==(that);
102    }
103
104    bool operator!=(const PhysRegId& that) const {
105        return RegId::operator!=(that);
106    }
107    /** @} */
108
109    /** @return true if it is an integer physical register. */
110    bool isIntPhysReg() const { return isIntReg(); }
111
112    /** @return true if it is a floating-point physical register. */
113    bool isFloatPhysReg() const { return isFloatReg(); }
114
115    /** @Return true if it is a  condition-code physical register. */
116    bool isCCPhysReg() const { return isCCReg(); }
117
118    /** @Return true if it is a vector physical register. */
119    bool isVectorPhysReg() const { return isVecReg(); }
120
121    /** @Return true if it is a vector element physical register. */
122    bool isVectorPhysElem() const { return isVecElem(); }
123
124    /** @Return true if it is a  condition-code physical register. */
125    bool isMiscPhysReg() const { return isMiscReg(); }
126
127    /**
128     * Returns true if this register is always associated to the same
129     * architectural register.
130     */
131    bool isFixedMapping() const
132    {
133        return !isRenameable();
134    }
135
136    /** Flat index accessor */
137    const PhysRegIndex& flatIndex() const { return flatIdx; }
138
139    static PhysRegId elemId(const PhysRegId* vid, ElemIndex elem)
140    {
141        assert(vid->isVectorPhysReg());
142        return PhysRegId(VecElemClass, vid->index(), elem);
143    }
144};
145
146/** Constant pointer definition.
147 * PhysRegIds only need to be created once and then we can just share
148 * pointers */
149using PhysRegIdPtr = const PhysRegId*;
150
151/** Struct that defines the information passed from fetch to decode. */
152template<class Impl>
153struct DefaultFetchDefaultDecode {
154    typedef typename Impl::DynInstPtr DynInstPtr;
155
156    int size;
157
158    DynInstPtr insts[Impl::MaxWidth];
159    Fault fetchFault;
160    InstSeqNum fetchFaultSN;
161    bool clearFetchFault;
162};
163
164/** Struct that defines the information passed from decode to rename. */
165template<class Impl>
166struct DefaultDecodeDefaultRename {
167    typedef typename Impl::DynInstPtr DynInstPtr;
168
169    int size;
170
171    DynInstPtr insts[Impl::MaxWidth];
172};
173
174/** Struct that defines the information passed from rename to IEW. */
175template<class Impl>
176struct DefaultRenameDefaultIEW {
177    typedef typename Impl::DynInstPtr DynInstPtr;
178
179    int size;
180
181    DynInstPtr insts[Impl::MaxWidth];
182};
183
184/** Struct that defines the information passed from IEW to commit. */
185template<class Impl>
186struct DefaultIEWDefaultCommit {
187    typedef typename Impl::DynInstPtr DynInstPtr;
188
189    int size;
190
191    DynInstPtr insts[Impl::MaxWidth];
192    DynInstPtr mispredictInst[Impl::MaxThreads];
193    Addr mispredPC[Impl::MaxThreads];
194    InstSeqNum squashedSeqNum[Impl::MaxThreads];
195    TheISA::PCState pc[Impl::MaxThreads];
196
197    bool squash[Impl::MaxThreads];
198    bool branchMispredict[Impl::MaxThreads];
199    bool branchTaken[Impl::MaxThreads];
200    bool includeSquashInst[Impl::MaxThreads];
201};
202
203template<class Impl>
204struct IssueStruct {
205    typedef typename Impl::DynInstPtr DynInstPtr;
206
207    int size;
208
209    DynInstPtr insts[Impl::MaxWidth];
210};
211
212/** Struct that defines all backwards communication. */
213template<class Impl>
214struct TimeBufStruct {
215    typedef typename Impl::DynInstPtr DynInstPtr;
216    struct decodeComm {
217        TheISA::PCState nextPC;
218        DynInstPtr mispredictInst;
219        DynInstPtr squashInst;
220        InstSeqNum doneSeqNum;
221        Addr mispredPC;
222        uint64_t branchAddr;
223        unsigned branchCount;
224        bool squash;
225        bool predIncorrect;
226        bool branchMispredict;
227        bool branchTaken;
228    };
229
230    decodeComm decodeInfo[Impl::MaxThreads];
231
232    struct renameComm {
233    };
234
235    renameComm renameInfo[Impl::MaxThreads];
236
237    struct iewComm {
238        // Also eventually include skid buffer space.
239        unsigned freeIQEntries;
240        unsigned freeLQEntries;
241        unsigned freeSQEntries;
242        unsigned dispatchedToLQ;
243        unsigned dispatchedToSQ;
244
245        unsigned iqCount;
246        unsigned ldstqCount;
247
248        unsigned dispatched;
249        bool usedIQ;
250        bool usedLSQ;
251    };
252
253    iewComm iewInfo[Impl::MaxThreads];
254
255    struct commitComm {
256        /////////////////////////////////////////////////////////////////////
257        // This code has been re-structured for better packing of variables
258        // instead of by stage which is the more logical way to arrange the
259        // data.
260        // F = Fetch
261        // D = Decode
262        // I = IEW
263        // R = Rename
264        // As such each member is annotated with who consumes it
265        // e.g. bool variable name // *F,R for Fetch and Rename
266        /////////////////////////////////////////////////////////////////////
267
268        /// The pc of the next instruction to execute. This is the next
269        /// instruction for a branch mispredict, but the same instruction for
270        /// order violation and the like
271        TheISA::PCState pc; // *F
272
273        /// Provide fetch the instruction that mispredicted, if this
274        /// pointer is not-null a misprediction occured
275        DynInstPtr mispredictInst;  // *F
276
277        /// Instruction that caused the a non-mispredict squash
278        DynInstPtr squashInst; // *F
279
280        /// Hack for now to send back a strictly ordered access to the
281        /// IEW stage.
282        DynInstPtr strictlyOrderedLoad; // *I
283
284        /// Communication specifically to the IQ to tell the IQ that it can
285        /// schedule a non-speculative instruction.
286        InstSeqNum nonSpecSeqNum; // *I
287
288        /// Represents the instruction that has either been retired or
289        /// squashed.  Similar to having a single bus that broadcasts the
290        /// retired or squashed sequence number.
291        InstSeqNum doneSeqNum; // *F, I
292
293        /// Tell Rename how many free entries it has in the ROB
294        unsigned freeROBEntries; // *R
295
296        bool squash; // *F, D, R, I
297        bool robSquashing; // *F, D, R, I
298
299        /// Rename should re-read number of free rob entries
300        bool usedROB; // *R
301
302        /// Notify Rename that the ROB is empty
303        bool emptyROB; // *R
304
305        /// Was the branch taken or not
306        bool branchTaken; // *F
307        /// If an interrupt is pending and fetch should stall
308        bool interruptPending; // *F
309        /// If the interrupt ended up being cleared before being handled
310        bool clearInterrupt; // *F
311
312        /// Hack for now to send back an strictly ordered access to
313        /// the IEW stage.
314        bool strictlyOrdered; // *I
315
316    };
317
318    commitComm commitInfo[Impl::MaxThreads];
319
320    bool decodeBlock[Impl::MaxThreads];
321    bool decodeUnblock[Impl::MaxThreads];
322    bool renameBlock[Impl::MaxThreads];
323    bool renameUnblock[Impl::MaxThreads];
324    bool iewBlock[Impl::MaxThreads];
325    bool iewUnblock[Impl::MaxThreads];
326};
327
328#endif //__CPU_O3_COMM_HH__
329