comm.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Nathanael Premillieu
43 */
44
45#ifndef __CPU_O3_COMM_HH__
46#define __CPU_O3_COMM_HH__
47
48#include <vector>
49
50#include "arch/types.hh"
51#include "base/types.hh"
52#include "cpu/inst_seq.hh"
53#include "sim/faults.hh"
54
55/** Physical register index type.
56 * Although the Impl might be a better for this, but there are a few classes
57 * that need this typedef yet are not templated on the Impl.
58 */
59using PhysRegIndex = short int;
60
61/** Physical register ID.
62 * Like a register ID but physical. The inheritance is private because the
63 * only relationship between this types is functional, and it is done to
64 * prevent code replication. */
65class PhysRegId : private RegId {
66  private:
67    PhysRegIndex flatIdx;
68
69  public:
70    explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {}
71
72    /** Scalar PhysRegId constructor. */
73    explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
74              PhysRegIndex _flatIdx)
75        : RegId(_regClass, _regIdx), flatIdx(_flatIdx)
76    {}
77
78    /** Visible RegId methods */
79    /** @{ */
80    using RegId::index;
81    using RegId::classValue;
82    using RegId::isZeroReg;
83    using RegId::className;
84     /** @} */
85    /**
86     * Explicit forward methods, to prevent comparisons of PhysRegId with
87     * RegIds.
88     */
89    /** @{ */
90    bool operator<(const PhysRegId& that) const {
91        return RegId::operator<(that);
92    }
93
94    bool operator==(const PhysRegId& that) const {
95        return RegId::operator==(that);
96    }
97
98    bool operator!=(const PhysRegId& that) const {
99        return RegId::operator!=(that);
100    }
101    /** @} */
102
103    /** @return true if it is an integer physical register. */
104    bool isIntPhysReg() const { return isIntReg(); }
105
106    /** @return true if it is a floating-point physical register. */
107    bool isFloatPhysReg() const { return isFloatReg(); }
108
109    /** @Return true if it is a  condition-code physical register. */
110    bool isCCPhysReg() const { return isCCReg(); }
111
112    /** @Return true if it is a  condition-code physical register. */
113    bool isMiscPhysReg() const { return isMiscReg(); }
114
115    /**
116     * Returns true if this register is always associated to the same
117     * architectural register.
118     */
119    bool isFixedMapping() const
120    {
121        return !isRenameable();
122    }
123
124    /** Flat index accessor */
125    const PhysRegIndex& flatIndex() const { return flatIdx; }
126};
127
128// PhysRegIds only need to be created once and then we can use the following
129// to work with them
130typedef const PhysRegId* PhysRegIdPtr;
131
132/** Struct that defines the information passed from fetch to decode. */
133template<class Impl>
134struct DefaultFetchDefaultDecode {
135    typedef typename Impl::DynInstPtr DynInstPtr;
136
137    int size;
138
139    DynInstPtr insts[Impl::MaxWidth];
140    Fault fetchFault;
141    InstSeqNum fetchFaultSN;
142    bool clearFetchFault;
143};
144
145/** Struct that defines the information passed from decode to rename. */
146template<class Impl>
147struct DefaultDecodeDefaultRename {
148    typedef typename Impl::DynInstPtr DynInstPtr;
149
150    int size;
151
152    DynInstPtr insts[Impl::MaxWidth];
153};
154
155/** Struct that defines the information passed from rename to IEW. */
156template<class Impl>
157struct DefaultRenameDefaultIEW {
158    typedef typename Impl::DynInstPtr DynInstPtr;
159
160    int size;
161
162    DynInstPtr insts[Impl::MaxWidth];
163};
164
165/** Struct that defines the information passed from IEW to commit. */
166template<class Impl>
167struct DefaultIEWDefaultCommit {
168    typedef typename Impl::DynInstPtr DynInstPtr;
169
170    int size;
171
172    DynInstPtr insts[Impl::MaxWidth];
173    DynInstPtr mispredictInst[Impl::MaxThreads];
174    Addr mispredPC[Impl::MaxThreads];
175    InstSeqNum squashedSeqNum[Impl::MaxThreads];
176    TheISA::PCState pc[Impl::MaxThreads];
177
178    bool squash[Impl::MaxThreads];
179    bool branchMispredict[Impl::MaxThreads];
180    bool branchTaken[Impl::MaxThreads];
181    bool includeSquashInst[Impl::MaxThreads];
182};
183
184template<class Impl>
185struct IssueStruct {
186    typedef typename Impl::DynInstPtr DynInstPtr;
187
188    int size;
189
190    DynInstPtr insts[Impl::MaxWidth];
191};
192
193/** Struct that defines all backwards communication. */
194template<class Impl>
195struct TimeBufStruct {
196    typedef typename Impl::DynInstPtr DynInstPtr;
197    struct decodeComm {
198        TheISA::PCState nextPC;
199        DynInstPtr mispredictInst;
200        DynInstPtr squashInst;
201        InstSeqNum doneSeqNum;
202        Addr mispredPC;
203        uint64_t branchAddr;
204        unsigned branchCount;
205        bool squash;
206        bool predIncorrect;
207        bool branchMispredict;
208        bool branchTaken;
209    };
210
211    decodeComm decodeInfo[Impl::MaxThreads];
212
213    struct renameComm {
214    };
215
216    renameComm renameInfo[Impl::MaxThreads];
217
218    struct iewComm {
219        // Also eventually include skid buffer space.
220        unsigned freeIQEntries;
221        unsigned freeLQEntries;
222        unsigned freeSQEntries;
223        unsigned dispatchedToLQ;
224        unsigned dispatchedToSQ;
225
226        unsigned iqCount;
227        unsigned ldstqCount;
228
229        unsigned dispatched;
230        bool usedIQ;
231        bool usedLSQ;
232    };
233
234    iewComm iewInfo[Impl::MaxThreads];
235
236    struct commitComm {
237        /////////////////////////////////////////////////////////////////////
238        // This code has been re-structured for better packing of variables
239        // instead of by stage which is the more logical way to arrange the
240        // data.
241        // F = Fetch
242        // D = Decode
243        // I = IEW
244        // R = Rename
245        // As such each member is annotated with who consumes it
246        // e.g. bool variable name // *F,R for Fetch and Rename
247        /////////////////////////////////////////////////////////////////////
248
249        /// The pc of the next instruction to execute. This is the next
250        /// instruction for a branch mispredict, but the same instruction for
251        /// order violation and the like
252        TheISA::PCState pc; // *F
253
254        /// Provide fetch the instruction that mispredicted, if this
255        /// pointer is not-null a misprediction occured
256        DynInstPtr mispredictInst;  // *F
257
258        /// Instruction that caused the a non-mispredict squash
259        DynInstPtr squashInst; // *F
260
261        /// Hack for now to send back a strictly ordered access to the
262        /// IEW stage.
263        DynInstPtr strictlyOrderedLoad; // *I
264
265        /// Communication specifically to the IQ to tell the IQ that it can
266        /// schedule a non-speculative instruction.
267        InstSeqNum nonSpecSeqNum; // *I
268
269        /// Represents the instruction that has either been retired or
270        /// squashed.  Similar to having a single bus that broadcasts the
271        /// retired or squashed sequence number.
272        InstSeqNum doneSeqNum; // *F, I
273
274        /// Tell Rename how many free entries it has in the ROB
275        unsigned freeROBEntries; // *R
276
277        bool squash; // *F, D, R, I
278        bool robSquashing; // *F, D, R, I
279
280        /// Rename should re-read number of free rob entries
281        bool usedROB; // *R
282
283        /// Notify Rename that the ROB is empty
284        bool emptyROB; // *R
285
286        /// Was the branch taken or not
287        bool branchTaken; // *F
288        /// If an interrupt is pending and fetch should stall
289        bool interruptPending; // *F
290        /// If the interrupt ended up being cleared before being handled
291        bool clearInterrupt; // *F
292
293        /// Hack for now to send back an strictly ordered access to
294        /// the IEW stage.
295        bool strictlyOrdered; // *I
296
297    };
298
299    commitComm commitInfo[Impl::MaxThreads];
300
301    bool decodeBlock[Impl::MaxThreads];
302    bool decodeUnblock[Impl::MaxThreads];
303    bool renameBlock[Impl::MaxThreads];
304    bool renameUnblock[Impl::MaxThreads];
305    bool iewBlock[Impl::MaxThreads];
306    bool iewUnblock[Impl::MaxThreads];
307};
308
309#endif //__CPU_O3_COMM_HH__
310