comm.hh revision 10824:308771bd2647 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_COMM_HH__
45#define __CPU_O3_COMM_HH__
46
47#include <vector>
48
49#include "arch/types.hh"
50#include "base/types.hh"
51#include "cpu/inst_seq.hh"
52#include "sim/faults.hh"
53
54// Typedef for physical register index type. Although the Impl would be the
55// most likely location for this, there are a few classes that need this
56// typedef yet are not templated on the Impl. For now it will be defined here.
57typedef short int PhysRegIndex;
58
59/** Struct that defines the information passed from fetch to decode. */
60template<class Impl>
61struct DefaultFetchDefaultDecode {
62    typedef typename Impl::DynInstPtr DynInstPtr;
63
64    int size;
65
66    DynInstPtr insts[Impl::MaxWidth];
67    Fault fetchFault;
68    InstSeqNum fetchFaultSN;
69    bool clearFetchFault;
70};
71
72/** Struct that defines the information passed from decode to rename. */
73template<class Impl>
74struct DefaultDecodeDefaultRename {
75    typedef typename Impl::DynInstPtr DynInstPtr;
76
77    int size;
78
79    DynInstPtr insts[Impl::MaxWidth];
80};
81
82/** Struct that defines the information passed from rename to IEW. */
83template<class Impl>
84struct DefaultRenameDefaultIEW {
85    typedef typename Impl::DynInstPtr DynInstPtr;
86
87    int size;
88
89    DynInstPtr insts[Impl::MaxWidth];
90};
91
92/** Struct that defines the information passed from IEW to commit. */
93template<class Impl>
94struct DefaultIEWDefaultCommit {
95    typedef typename Impl::DynInstPtr DynInstPtr;
96
97    int size;
98
99    DynInstPtr insts[Impl::MaxWidth];
100    DynInstPtr mispredictInst[Impl::MaxThreads];
101    Addr mispredPC[Impl::MaxThreads];
102    InstSeqNum squashedSeqNum[Impl::MaxThreads];
103    TheISA::PCState pc[Impl::MaxThreads];
104
105    bool squash[Impl::MaxThreads];
106    bool branchMispredict[Impl::MaxThreads];
107    bool branchTaken[Impl::MaxThreads];
108    bool includeSquashInst[Impl::MaxThreads];
109};
110
111template<class Impl>
112struct IssueStruct {
113    typedef typename Impl::DynInstPtr DynInstPtr;
114
115    int size;
116
117    DynInstPtr insts[Impl::MaxWidth];
118};
119
120/** Struct that defines all backwards communication. */
121template<class Impl>
122struct TimeBufStruct {
123    typedef typename Impl::DynInstPtr DynInstPtr;
124    struct decodeComm {
125        TheISA::PCState nextPC;
126        DynInstPtr mispredictInst;
127        DynInstPtr squashInst;
128        InstSeqNum doneSeqNum;
129        Addr mispredPC;
130        uint64_t branchAddr;
131        unsigned branchCount;
132        bool squash;
133        bool predIncorrect;
134        bool branchMispredict;
135        bool branchTaken;
136    };
137
138    decodeComm decodeInfo[Impl::MaxThreads];
139
140    struct renameComm {
141    };
142
143    renameComm renameInfo[Impl::MaxThreads];
144
145    struct iewComm {
146        // Also eventually include skid buffer space.
147        unsigned freeIQEntries;
148        unsigned freeLQEntries;
149        unsigned freeSQEntries;
150        unsigned dispatchedToLQ;
151        unsigned dispatchedToSQ;
152
153        unsigned iqCount;
154        unsigned ldstqCount;
155
156        unsigned dispatched;
157        bool usedIQ;
158        bool usedLSQ;
159    };
160
161    iewComm iewInfo[Impl::MaxThreads];
162
163    struct commitComm {
164        /////////////////////////////////////////////////////////////////////
165        // This code has been re-structured for better packing of variables
166        // instead of by stage which is the more logical way to arrange the
167        // data.
168        // F = Fetch
169        // D = Decode
170        // I = IEW
171        // R = Rename
172        // As such each member is annotated with who consumes it
173        // e.g. bool variable name // *F,R for Fetch and Rename
174        /////////////////////////////////////////////////////////////////////
175
176        /// The pc of the next instruction to execute. This is the next
177        /// instruction for a branch mispredict, but the same instruction for
178        /// order violation and the like
179        TheISA::PCState pc; // *F
180
181        /// Provide fetch the instruction that mispredicted, if this
182        /// pointer is not-null a misprediction occured
183        DynInstPtr mispredictInst;  // *F
184
185        /// Instruction that caused the a non-mispredict squash
186        DynInstPtr squashInst; // *F
187
188        /// Hack for now to send back a strictly ordered access to the
189        /// IEW stage.
190        DynInstPtr strictlyOrderedLoad; // *I
191
192        /// Communication specifically to the IQ to tell the IQ that it can
193        /// schedule a non-speculative instruction.
194        InstSeqNum nonSpecSeqNum; // *I
195
196        /// Represents the instruction that has either been retired or
197        /// squashed.  Similar to having a single bus that broadcasts the
198        /// retired or squashed sequence number.
199        InstSeqNum doneSeqNum; // *F, I
200
201        /// Tell Rename how many free entries it has in the ROB
202        unsigned freeROBEntries; // *R
203
204        bool squash; // *F, D, R, I
205        bool robSquashing; // *F, D, R, I
206
207        /// Rename should re-read number of free rob entries
208        bool usedROB; // *R
209
210        /// Notify Rename that the ROB is empty
211        bool emptyROB; // *R
212
213        /// Was the branch taken or not
214        bool branchTaken; // *F
215        /// If an interrupt is pending and fetch should stall
216        bool interruptPending; // *F
217        /// If the interrupt ended up being cleared before being handled
218        bool clearInterrupt; // *F
219
220        /// Hack for now to send back an strictly ordered access to
221        /// the IEW stage.
222        bool strictlyOrdered; // *I
223
224    };
225
226    commitComm commitInfo[Impl::MaxThreads];
227
228    bool decodeBlock[Impl::MaxThreads];
229    bool decodeUnblock[Impl::MaxThreads];
230    bool renameBlock[Impl::MaxThreads];
231    bool renameUnblock[Impl::MaxThreads];
232    bool iewBlock[Impl::MaxThreads];
233    bool iewUnblock[Impl::MaxThreads];
234};
235
236#endif //__CPU_O3_COMM_HH__
237