SConscript revision 4776 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31import sys
32
33Import('*')
34
35if 'O3CPU' in env['CPU_MODELS']:
36    SimObject('FUPool.py')
37    SimObject('FuncUnitConfig.py')
38    SimObject('O3CPU.py')
39
40    Source('base_dyn_inst.cc')
41    Source('bpred_unit.cc')
42    Source('commit.cc')
43    Source('cpu.cc')
44    Source('decode.cc')
45    Source('fetch.cc')
46    Source('free_list.cc')
47    Source('fu_pool.cc')
48    Source('iew.cc')
49    Source('inst_queue.cc')
50    Source('lsq.cc')
51    Source('lsq_unit.cc')
52    Source('mem_dep_unit.cc')
53    Source('rename.cc')
54    Source('rename_map.cc')
55    Source('rob.cc')
56    Source('scoreboard.cc')
57    Source('store_set.cc')
58
59    if env['TARGET_ISA'] == 'alpha':
60        Source('alpha/cpu.cc')
61        Source('alpha/cpu_builder.cc')
62        Source('alpha/dyn_inst.cc')
63        Source('alpha/thread_context.cc')
64    elif env['TARGET_ISA'] == 'mips':
65        Source('mips/cpu.cc')
66        Source('mips/cpu_builder.cc')
67        Source('mips/dyn_inst.cc')
68        Source('mips/thread_context.cc')
69    elif env['TARGET_ISA'] == 'sparc':
70        Source('sparc/cpu.cc')
71        Source('sparc/cpu_builder.cc')
72        Source('sparc/dyn_inst.cc')
73        Source('sparc/thread_context.cc')
74    else:
75        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
76
77    if env['USE_CHECKER']:
78        SimObject('O3Checker.py')
79        Source('checker_builder.cc')
80
81if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
82    Source('2bit_local_pred.cc')
83    Source('btb.cc')
84    Source('ras.cc')
85    Source('tournament_pred.cc')
86
87