SConscript revision 4484
112120Sar4jc@virginia.edu# -*- mode:python -*- 212120Sar4jc@virginia.edu 312120Sar4jc@virginia.edu# Copyright (c) 2006 The Regents of The University of Michigan 412120Sar4jc@virginia.edu# All rights reserved. 512120Sar4jc@virginia.edu# 612120Sar4jc@virginia.edu# Redistribution and use in source and binary forms, with or without 712120Sar4jc@virginia.edu# modification, are permitted provided that the following conditions are 812120Sar4jc@virginia.edu# met: redistributions of source code must retain the above copyright 912120Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer; 1012120Sar4jc@virginia.edu# redistributions in binary form must reproduce the above copyright 1112120Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer in the 1212120Sar4jc@virginia.edu# documentation and/or other materials provided with the distribution; 1312120Sar4jc@virginia.edu# neither the name of the copyright holders nor the names of its 1412120Sar4jc@virginia.edu# contributors may be used to endorse or promote products derived from 1512120Sar4jc@virginia.edu# this software without specific prior written permission. 1612120Sar4jc@virginia.edu# 1712120Sar4jc@virginia.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812120Sar4jc@virginia.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912120Sar4jc@virginia.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012120Sar4jc@virginia.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112120Sar4jc@virginia.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212120Sar4jc@virginia.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312120Sar4jc@virginia.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412120Sar4jc@virginia.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512120Sar4jc@virginia.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612120Sar4jc@virginia.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712120Sar4jc@virginia.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812120Sar4jc@virginia.edu# 2912120Sar4jc@virginia.edu# Authors: Nathan Binkert 3012120Sar4jc@virginia.edu 3112120Sar4jc@virginia.eduimport sys 3212120Sar4jc@virginia.edu 3312120Sar4jc@virginia.eduImport('*') 3412120Sar4jc@virginia.edu 3512120Sar4jc@virginia.eduif 'O3CPU' in env['CPU_MODELS']: 3612120Sar4jc@virginia.edu Source('base_dyn_inst.cc') 3712120Sar4jc@virginia.edu Source('bpred_unit.cc') 3812120Sar4jc@virginia.edu Source('commit.cc') 3912120Sar4jc@virginia.edu Source('cpu.cc') 4012120Sar4jc@virginia.edu Source('decode.cc') 4112120Sar4jc@virginia.edu Source('fetch.cc') 4212120Sar4jc@virginia.edu Source('free_list.cc') 4312120Sar4jc@virginia.edu Source('fu_pool.cc') 4412120Sar4jc@virginia.edu Source('iew.cc') 4512120Sar4jc@virginia.edu Source('inst_queue.cc') 4612120Sar4jc@virginia.edu Source('lsq.cc') 4712120Sar4jc@virginia.edu Source('lsq_unit.cc') 4812120Sar4jc@virginia.edu Source('mem_dep_unit.cc') 4912120Sar4jc@virginia.edu Source('rename.cc') 5012120Sar4jc@virginia.edu Source('rename_map.cc') 5112120Sar4jc@virginia.edu Source('rob.cc') 5212120Sar4jc@virginia.edu Source('scoreboard.cc') 5312120Sar4jc@virginia.edu Source('store_set.cc') 5412120Sar4jc@virginia.edu 5512120Sar4jc@virginia.edu if env['TARGET_ISA'] == 'alpha': 5612120Sar4jc@virginia.edu Source('alpha/cpu.cc') 5712120Sar4jc@virginia.edu Source('alpha/cpu_builder.cc') 5812120Sar4jc@virginia.edu Source('alpha/dyn_inst.cc') 5912120Sar4jc@virginia.edu Source('alpha/thread_context.cc') 6012120Sar4jc@virginia.edu elif env['TARGET_ISA'] == 'mips': 6112120Sar4jc@virginia.edu Source('mips/cpu.cc') 6212120Sar4jc@virginia.edu Source('mips/cpu_builder.cc') 6312120Sar4jc@virginia.edu Source('mips/dyn_inst.cc') 6412120Sar4jc@virginia.edu Source('mips/thread_context.cc') 6512120Sar4jc@virginia.edu elif env['TARGET_ISA'] == 'sparc': 6612120Sar4jc@virginia.edu Source('sparc/cpu.cc') 6712120Sar4jc@virginia.edu Source('sparc/cpu_builder.cc') 6812120Sar4jc@virginia.edu Source('sparc/dyn_inst.cc') 6912120Sar4jc@virginia.edu Source('sparc/thread_context.cc') 7012120Sar4jc@virginia.edu else: 7112120Sar4jc@virginia.edu sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) 7212120Sar4jc@virginia.edu 7312120Sar4jc@virginia.edu if env['USE_CHECKER']: 7412120Sar4jc@virginia.edu Source('checker_builder.cc') 7512120Sar4jc@virginia.edu 7612120Sar4jc@virginia.eduif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 7712120Sar4jc@virginia.edu Source('2bit_local_pred.cc') 7812120Sar4jc@virginia.edu Source('btb.cc') 7912120Sar4jc@virginia.edu Source('ras.cc') 8012120Sar4jc@virginia.edu Source('tournament_pred.cc') 8112120Sar4jc@virginia.edu 8212120Sar4jc@virginia.edu