SConscript revision 4202:f7a05daec670
1545SN/A# -*- mode:python -*-
28948SN/A
38948SN/A# Copyright (c) 2006 The Regents of The University of Michigan
48948SN/A# All rights reserved.
58948SN/A#
68948SN/A# Redistribution and use in source and binary forms, with or without
78948SN/A# modification, are permitted provided that the following conditions are
88948SN/A# met: redistributions of source code must retain the above copyright
98948SN/A# notice, this list of conditions and the following disclaimer;
108948SN/A# redistributions in binary form must reproduce the above copyright
118948SN/A# notice, this list of conditions and the following disclaimer in the
128948SN/A# documentation and/or other materials provided with the distribution;
138948SN/A# neither the name of the copyright holders nor the names of its
142512SN/A# contributors may be used to endorse or promote products derived from
15545SN/A# this software without specific prior written permission.
16545SN/A#
17545SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18545SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19545SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20545SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21545SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22545SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23545SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24545SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25545SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26545SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27545SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28545SN/A#
29545SN/A# Authors: Nathan Binkert
30545SN/A
31545SN/Aimport sys
32545SN/A
33545SN/AImport('*')
34545SN/A
35545SN/Aif 'O3CPU' in env['CPU_MODELS']:
36545SN/A    Source('base_dyn_inst.cc')
37545SN/A    Source('bpred_unit.cc')
38545SN/A    Source('commit.cc')
392665SN/A    Source('cpu.cc')
402665SN/A    Source('decode.cc')
412665SN/A    Source('fetch.cc')
429166Sandreas.hansson@arm.com    Source('free_list.cc')
43545SN/A    Source('fu_pool.cc')
44545SN/A    Source('iew.cc')
453090SN/A    Source('inst_queue.cc')
468232SN/A    Source('lsq.cc')
479152Satgutier@umich.edu    Source('lsq_unit.cc')
489016Sandreas.hansson@arm.com    Source('mem_dep_unit.cc')
492901SN/A    Source('rename.cc')
50545SN/A    Source('rename_map.cc')
519165Sandreas.hansson@arm.com    Source('rob.cc')
529307Sandreas.hansson@arm.com    Source('scoreboard.cc')
539307Sandreas.hansson@arm.com    Source('store_set.cc')
549133Satgutier@umich.edu
559165Sandreas.hansson@arm.com    if env['TARGET_ISA'] == 'alpha':
562489SN/A        Source('alpha/cpu.cc')
572489SN/A        Source('alpha/cpu_builder.cc')
589166Sandreas.hansson@arm.com        Source('alpha/dyn_inst.cc')
599166Sandreas.hansson@arm.com        Source('alpha/thread_context.cc')
609166Sandreas.hansson@arm.com    elif env['TARGET_ISA'] == 'mips':
619166Sandreas.hansson@arm.com        Source('mips/cpu.cc')
629166Sandreas.hansson@arm.com        Source('mips/cpu_builder.cc')
639166Sandreas.hansson@arm.com        Source('mips/dyn_inst.cc')
649166Sandreas.hansson@arm.com        Source('mips/thread_context.cc')
659166Sandreas.hansson@arm.com    elif env['TARGET_ISA'] == 'sparc':
669166Sandreas.hansson@arm.com        Source('sparc/cpu.cc')
679166Sandreas.hansson@arm.com        Source('sparc/cpu_builder.cc')
689166Sandreas.hansson@arm.com        Source('sparc/dyn_inst.cc')
699166Sandreas.hansson@arm.com        Source('sparc/thread_context.cc')
709166Sandreas.hansson@arm.com    else:
719166Sandreas.hansson@arm.com        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
729166Sandreas.hansson@arm.com
739166Sandreas.hansson@arm.com    if env['USE_CHECKER']:
749166Sandreas.hansson@arm.com        Source('checker_builder.cc')
759166Sandreas.hansson@arm.com
769166Sandreas.hansson@arm.comif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
779166Sandreas.hansson@arm.com    Source('2bit_local_pred.cc')
789166Sandreas.hansson@arm.com    Source('btb.cc')
799166Sandreas.hansson@arm.com    Source('ras.cc')
809166Sandreas.hansson@arm.com    Source('tournament_pred.cc')
819166Sandreas.hansson@arm.com
829166Sandreas.hansson@arm.com