SConscript revision 6168 
12810SN/A# -*- mode:python -*-
22810SN/A
32810SN/A# Copyright (c) 2006 The Regents of The University of Michigan
42810SN/A# All rights reserved.
52810SN/A#
62810SN/A# Redistribution and use in source and binary forms, with or without
72810SN/A# modification, are permitted provided that the following conditions are
82810SN/A# met: redistributions of source code must retain the above copyright
92810SN/A# notice, this list of conditions and the following disclaimer;
102810SN/A# redistributions in binary form must reproduce the above copyright
112810SN/A# notice, this list of conditions and the following disclaimer in the
122810SN/A# documentation and/or other materials provided with the distribution;
132810SN/A# neither the name of the copyright holders nor the names of its
142810SN/A# contributors may be used to endorse or promote products derived from
152810SN/A# this software without specific prior written permission.
162810SN/A#
172810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282810SN/A#
292810SN/A# Authors: Nathan Binkert
302810SN/A
312810SN/Aimport sys
322810SN/A
333861SN/AImport('*')
342810SN/A
352810SN/Aif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
362810SN/A    Source('2bit_local_pred.cc')
372810SN/A    Source('btb.cc')
382810SN/A    Source('ras.cc')
395338Sstever@gmail.com    Source('tournament_pred.cc')
408831Smrinmoy.ghosh@arm.com
418831Smrinmoy.ghosh@arm.com    TraceFlag('CommitRate')
422810SN/A    TraceFlag('IEW')
433861SN/A    TraceFlag('IQ')
442810SN/A
452810SN/Aif 'O3CPU' in env['CPU_MODELS']:
462810SN/A    SimObject('FUPool.py')
478831Smrinmoy.ghosh@arm.com    SimObject('FuncUnitConfig.py')
482810SN/A    SimObject('O3CPU.py')
492810SN/A
502810SN/A    Source('base_dyn_inst.cc')
513349SN/A    Source('bpred_unit.cc')
522810SN/A    Source('commit.cc')
532810SN/A    Source('cpu.cc')
542810SN/A    Source('cpu_builder.cc')
552810SN/A    Source('decode.cc')
56    Source('dyn_inst.cc')
57    Source('fetch.cc')
58    Source('free_list.cc')
59    Source('fu_pool.cc')
60    Source('iew.cc')
61    Source('inst_queue.cc')
62    Source('lsq.cc')
63    Source('lsq_unit.cc')
64    Source('mem_dep_unit.cc')
65    Source('rename.cc')
66    Source('rename_map.cc')
67    Source('rob.cc')
68    Source('scoreboard.cc')
69    Source('store_set.cc')
70    Source('thread_context.cc')
71
72    TraceFlag('FreeList')
73    TraceFlag('LSQ')
74    TraceFlag('LSQUnit')
75    TraceFlag('MemDepUnit')
76    TraceFlag('O3CPU')
77    TraceFlag('ROB')
78    TraceFlag('Rename')
79    TraceFlag('Scoreboard')
80    TraceFlag('StoreSet')
81    TraceFlag('Writeback')
82
83    CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
84        'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
85        'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
86
87    if env['USE_CHECKER']:
88        SimObject('O3Checker.py')
89        Source('checker_builder.cc')
90