SConscript revision 5649
12SN/A# -*- mode:python -*- 21762SN/A 32SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42SN/A# All rights reserved. 52SN/A# 62SN/A# Redistribution and use in source and binary forms, with or without 72SN/A# modification, are permitted provided that the following conditions are 82SN/A# met: redistributions of source code must retain the above copyright 92SN/A# notice, this list of conditions and the following disclaimer; 102SN/A# redistributions in binary form must reproduce the above copyright 112SN/A# notice, this list of conditions and the following disclaimer in the 122SN/A# documentation and/or other materials provided with the distribution; 132SN/A# neither the name of the copyright holders nor the names of its 142SN/A# contributors may be used to endorse or promote products derived from 152SN/A# this software without specific prior written permission. 162SN/A# 172SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Nathan Binkert 302665Ssaidi@eecs.umich.edu 312SN/Aimport sys 322SN/A 332623SN/AImport('*') 342623SN/A 352SN/Aif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 364182Sgblack@eecs.umich.edu Source('2bit_local_pred.cc') 371354SN/A Source('btb.cc') 381858SN/A Source('ras.cc') 391717SN/A Source('tournament_pred.cc') 402683Sktlim@umich.edu 411354SN/A TraceFlag('CommitRate') 421354SN/A TraceFlag('IEW') 432387SN/A TraceFlag('IQ') 442387SN/A 452387SN/Aif 'O3CPU' in env['CPU_MODELS']: 4656SN/A SimObject('FUPool.py') 472SN/A SimObject('FuncUnitConfig.py') 482SN/A SimObject('O3CPU.py') 491858SN/A 502SN/A Source('base_dyn_inst.cc') 513453Sgblack@eecs.umich.edu Source('bpred_unit.cc') 523453Sgblack@eecs.umich.edu Source('commit.cc') 533453Sgblack@eecs.umich.edu Source('cpu.cc') 543453Sgblack@eecs.umich.edu Source('cpu_builder.cc') 553453Sgblack@eecs.umich.edu Source('decode.cc') 562462SN/A Source('dyn_inst.cc') 572SN/A Source('fetch.cc') 58715SN/A Source('free_list.cc') 59715SN/A Source('fu_pool.cc') 60715SN/A Source('iew.cc') 61715SN/A Source('inst_queue.cc') 622SN/A Source('lsq.cc') 632SN/A Source('lsq_unit.cc') 643960Sgblack@eecs.umich.edu Source('mem_dep_unit.cc') 653960Sgblack@eecs.umich.edu Source('rename.cc') 663960Sgblack@eecs.umich.edu Source('rename_map.cc') 674182Sgblack@eecs.umich.edu Source('rob.cc') 684182Sgblack@eecs.umich.edu Source('scoreboard.cc') 694182Sgblack@eecs.umich.edu Source('store_set.cc') 704182Sgblack@eecs.umich.edu Source('thread_context.cc') 712680Sktlim@umich.edu 72237SN/A TraceFlag('FreeList') 732SN/A TraceFlag('LSQ') 742SN/A TraceFlag('LSQUnit') 752SN/A TraceFlag('MemDepUnit') 762SN/A TraceFlag('O3CPU') 772SN/A TraceFlag('ROB') 782420SN/A TraceFlag('Rename') 792623SN/A TraceFlag('Scoreboard') 802SN/A TraceFlag('StoreSet') 812107SN/A TraceFlag('Writeback') 822159SN/A 832455SN/A CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 842455SN/A 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 852386SN/A 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 862623SN/A 872SN/A if env['USE_CHECKER']: 881371SN/A SimObject('O3Checker.py') 892SN/A Source('checker_builder.cc') 902SN/A