SConscript revision 5222 
14202Sbinkertn@umich.edu# -*- mode:python -*-
24202Sbinkertn@umich.edu
34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
44202Sbinkertn@umich.edu# All rights reserved.
54202Sbinkertn@umich.edu#
64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without
74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are
84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright
94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer;
104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright
114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the
124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution;
134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its
144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from
154202Sbinkertn@umich.edu# this software without specific prior written permission.
164202Sbinkertn@umich.edu#
174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284202Sbinkertn@umich.edu#
294202Sbinkertn@umich.edu# Authors: Nathan Binkert
304202Sbinkertn@umich.edu
314202Sbinkertn@umich.eduimport sys
324202Sbinkertn@umich.edu
334202Sbinkertn@umich.eduImport('*')
344202Sbinkertn@umich.edu
354202Sbinkertn@umich.eduif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
364202Sbinkertn@umich.edu    Source('2bit_local_pred.cc')
374202Sbinkertn@umich.edu    Source('btb.cc')
38    Source('ras.cc')
39    Source('tournament_pred.cc')
40
41    TraceFlag('CommitRate')
42    TraceFlag('IEW')
43    TraceFlag('IQ')
44
45if 'O3CPU' in env['CPU_MODELS']:
46    SimObject('FUPool.py')
47    SimObject('FuncUnitConfig.py')
48    SimObject('O3CPU.py')
49
50    Source('base_dyn_inst.cc')
51    Source('bpred_unit.cc')
52    Source('commit.cc')
53    Source('cpu.cc')
54    Source('decode.cc')
55    Source('fetch.cc')
56    Source('free_list.cc')
57    Source('fu_pool.cc')
58    Source('iew.cc')
59    Source('inst_queue.cc')
60    Source('lsq.cc')
61    Source('lsq_unit.cc')
62    Source('mem_dep_unit.cc')
63    Source('rename.cc')
64    Source('rename_map.cc')
65    Source('rob.cc')
66    Source('scoreboard.cc')
67    Source('store_set.cc')
68
69    TraceFlag('FreeList')
70    TraceFlag('LSQ')
71    TraceFlag('LSQUnit')
72    TraceFlag('MemDepUnit')
73    TraceFlag('O3CPU')
74    TraceFlag('ROB')
75    TraceFlag('Rename')
76    TraceFlag('Scoreboard')
77    TraceFlag('StoreSet')
78    TraceFlag('Writeback')
79
80    CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
81        'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
82        'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
83
84    if env['TARGET_ISA'] == 'alpha':
85        Source('alpha/cpu.cc')
86        Source('alpha/cpu_builder.cc')
87        Source('alpha/dyn_inst.cc')
88        Source('alpha/thread_context.cc')
89    elif env['TARGET_ISA'] == 'mips':
90        Source('mips/cpu.cc')
91        Source('mips/cpu_builder.cc')
92        Source('mips/dyn_inst.cc')
93        Source('mips/thread_context.cc')
94    elif env['TARGET_ISA'] == 'sparc':
95        Source('sparc/cpu.cc')
96        Source('sparc/cpu_builder.cc')
97        Source('sparc/dyn_inst.cc')
98        Source('sparc/thread_context.cc')
99    else:
100        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
101
102    if env['USE_CHECKER']:
103        SimObject('O3Checker.py')
104        Source('checker_builder.cc')
105