O3CPU.py revision 8807:35e77c938919
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * 34 35if buildEnv['USE_CHECKER']: 36 from O3Checker import O3Checker 37 38class DerivO3CPU(BaseCPU): 39 type = 'DerivO3CPU' 40 activity = Param.Unsigned(0, "Initial count") 41 42 if buildEnv['USE_CHECKER']: 43 checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 44 exitOnError=False, 45 updateOnError=True, 46 warnOnlyOnLoadError=False), 47 "checker") 48 checker.itb = Parent.itb 49 checker.dtb = Parent.dtb 50 51 cachePorts = Param.Unsigned(200, "Cache Ports") 52 53 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 54 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 55 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 56 "delay") 57 commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 58 fetchWidth = Param.Unsigned(8, "Fetch width") 59 60 renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 61 iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 62 "delay") 63 commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 64 fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 65 decodeWidth = Param.Unsigned(8, "Decode width") 66 67 iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 68 "delay") 69 commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 70 decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 71 renameWidth = Param.Unsigned(8, "Rename width") 72 73 commitToIEWDelay = Param.Unsigned(1, "Commit to " 74 "Issue/Execute/Writeback delay") 75 renameToIEWDelay = Param.Unsigned(2, "Rename to " 76 "Issue/Execute/Writeback delay") 77 issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 78 "to the IEW stage)") 79 dispatchWidth = Param.Unsigned(8, "Dispatch width") 80 issueWidth = Param.Unsigned(8, "Issue width") 81 wbWidth = Param.Unsigned(8, "Writeback width") 82 wbDepth = Param.Unsigned(1, "Writeback depth") 83 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 84 85 iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 86 "delay") 87 renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 88 commitWidth = Param.Unsigned(8, "Commit width") 89 squashWidth = Param.Unsigned(8, "Squash width") 90 trapLatency = Param.Tick(13, "Trap latency") 91 fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 92 93 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 94 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 95 96 predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 97 localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 98 localCtrBits = Param.Unsigned(2, "Bits per counter") 99 localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 100 localHistoryBits = Param.Unsigned(11, "Bits for the local history") 101 globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 102 globalCtrBits = Param.Unsigned(2, "Bits per counter") 103 globalHistoryBits = Param.Unsigned(13, "Bits of history") 104 choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 105 choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 106 107 BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 108 BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 109 110 RASSize = Param.Unsigned(16, "RAS size") 111 112 LQEntries = Param.Unsigned(32, "Number of load queue entries") 113 SQEntries = Param.Unsigned(32, "Number of store queue entries") 114 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 115 LSQCheckLoads = Param.Bool(True, 116 "Should dependency violations be checked for loads & stores or just stores") 117 store_set_clear_period = Param.Unsigned(250000, 118 "Number of load/store insts before the dep predictor should be invalidated") 119 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 120 SSITSize = Param.Unsigned(1024, "Store set ID table size") 121 122 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 123 124 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 125 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 126 "registers") 127 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 128 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 129 130 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 131 132 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 133 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 141 142 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 143 "Enable TSO Memory model") 144