O3CPU.py revision 12109:f29e9c5418aa 
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39# Authors: Kevin Lim
40
41from m5.defines import buildEnv
42from m5.params import *
43from m5.proxy import *
44from BaseCPU import BaseCPU
45from FUPool import *
46from O3Checker import O3Checker
47from BranchPredictor import *
48
49class DerivO3CPU(BaseCPU):
50    type = 'DerivO3CPU'
51    cxx_header = 'cpu/o3/deriv.hh'
52
53    @classmethod
54    def memory_mode(cls):
55        return 'timing'
56
57    @classmethod
58    def require_caches(cls):
59        return True
60
61    @classmethod
62    def support_take_over(cls):
63        return True
64
65    activity = Param.Unsigned(0, "Initial count")
66
67    cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
68          "Constrains stores only. Loads are constrained by load FUs.")
69
70    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
71    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
72    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
73                                   "delay")
74    commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
75    fetchWidth = Param.Unsigned(8, "Fetch width")
76    fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
77    fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
78                                    "per-thread")
79
80    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
81    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
82                                    "delay")
83    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
84    fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
85    decodeWidth = Param.Unsigned(8, "Decode width")
86
87    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
88                                    "delay")
89    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
90    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
91    renameWidth = Param.Unsigned(8, "Rename width")
92
93    commitToIEWDelay = Param.Cycles(1, "Commit to "
94               "Issue/Execute/Writeback delay")
95    renameToIEWDelay = Param.Cycles(2, "Rename to "
96               "Issue/Execute/Writeback delay")
97    issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
98              "to the IEW stage)")
99    dispatchWidth = Param.Unsigned(8, "Dispatch width")
100    issueWidth = Param.Unsigned(8, "Issue width")
101    wbWidth = Param.Unsigned(8, "Writeback width")
102    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
103
104    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
105               "delay")
106    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
107    commitWidth = Param.Unsigned(8, "Commit width")
108    squashWidth = Param.Unsigned(8, "Squash width")
109    trapLatency = Param.Cycles(13, "Trap latency")
110    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
111
112    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
113    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
114
115    LQEntries = Param.Unsigned(32, "Number of load queue entries")
116    SQEntries = Param.Unsigned(32, "Number of store queue entries")
117    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
118    LSQCheckLoads = Param.Bool(True,
119        "Should dependency violations be checked for loads & stores or just stores")
120    store_set_clear_period = Param.Unsigned(250000,
121            "Number of load/store insts before the dep predictor should be invalidated")
122    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
123    SSITSize = Param.Unsigned(1024, "Store set ID table size")
124
125    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
126
127    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
128    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
129                                      "registers")
130    # most ISAs don't use condition-code regs, so default is 0
131    _defaultNumPhysCCRegs = 0
132    if buildEnv['TARGET_ISA'] in ('arm','x86'):
133        # For x86, each CC reg is used to hold only a subset of the
134        # flags, so we need 4-5 times the number of CC regs as
135        # physical integer regs to be sure we don't run out.  In
136        # typical real machines, CC regs are not explicitly renamed
137        # (it's a side effect of int reg renaming), so they should
138        # never be the bottleneck here.
139        _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
140    numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
141                                      "registers")
142    numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
143                                   "Number of physical cc registers")
144    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
145    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
146
147    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
148    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
149    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
150    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
151    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
152    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
153    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
154    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
155    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
156
157    branchPred = Param.BranchPredictor(TournamentBP(numThreads =
158                                                       Parent.numThreads),
159                                       "Branch Predictor")
160    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
161                          "Enable TSO Memory model")
162
163    def addCheckerCpu(self):
164        if buildEnv['TARGET_ISA'] in ['arm']:
165            from ArmTLB import ArmTLB
166
167            self.checker = O3Checker(workload=self.workload,
168                                     exitOnError=False,
169                                     updateOnError=True,
170                                     warnOnlyOnLoadError=True)
171            self.checker.itb = ArmTLB(size = self.itb.size)
172            self.checker.dtb = ArmTLB(size = self.dtb.size)
173            self.checker.cpu_id = self.cpu_id
174
175        else:
176            print "ERROR: Checker only supported under ARM ISA!"
177            exit(1)
178