scoreboard.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40/**
41 * @file
42 *
43 *  A simple instruction scoreboard for tracking dependencies in Execute.
44 */
45
46#ifndef __CPU_MINOR_SCOREBOARD_HH__
47#define __CPU_MINOR_SCOREBOARD_HH__
48
49#include "cpu/minor/cpu.hh"
50#include "cpu/minor/dyn_inst.hh"
51#include "cpu/minor/trace.hh"
52
53namespace Minor
54{
55
56/** A scoreboard of register dependencies including, for each register:
57 *  The number of in-flight instructions which will generate a result for
58 *  this register */
59class Scoreboard : public Named
60{
61  public:
62    /** The number of registers in the Scoreboard.  These
63     *  are just the integer, CC and float registers packed
64     *  together with integer regs in the range [0,NumIntRegs-1],
65     *  CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1]
66     *  and float regs in the range
67     *  [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
68    const unsigned numRegs;
69
70    /** Type to use when indexing numResults */
71    typedef unsigned short int Index;
72
73    /** Count of the number of in-flight instructions that
74     *  have results for each register */
75    std::vector<Index> numResults;
76
77    /** Count of the number of results which can't be predicted */
78    std::vector<Index> numUnpredictableResults;
79
80    /** Index of the FU generating this result */
81    std::vector<int> fuIndices;
82
83    /** The estimated cycle number that the result will be presented.
84     *  This can be offset from to allow forwarding to be simulated as
85     *  long as instruction completion is *strictly* in order with
86     *  respect to instructions with unpredictable result timing */
87    std::vector<Cycles> returnCycle;
88
89    /** The execute sequence number of the most recent inst to generate this
90     *  register value */
91    std::vector<InstSeqNum> writingInst;
92
93  public:
94    Scoreboard(const std::string &name) :
95        Named(name),
96        numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
97            TheISA::NumFloatRegs),
98        numResults(numRegs, 0),
99        numUnpredictableResults(numRegs, 0),
100        fuIndices(numRegs, 0),
101        returnCycle(numRegs, Cycles(0)),
102        writingInst(numRegs, 0)
103    { }
104
105  public:
106    /** Sets scoreboard_index to the index into numResults of the
107     *  given register index.  Returns true if the given register
108     *  is in the scoreboard and false if it isn't */
109    bool findIndex(const RegId& reg, Index &scoreboard_index);
110
111    /** Mark up an instruction's effects by incrementing
112     *  numResults counts.  If mark_unpredictable is true, the inst's
113     *  destination registers are marked as being unpredictable without
114     *  an estimated retire time */
115    void markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
116        ThreadContext *thread_context, bool mark_unpredictable);
117
118    /** Clear down the dependencies for this instruction.  clear_unpredictable
119     *  must match mark_unpredictable for the same inst. */
120    void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable);
121
122    /** Returns the exec sequence number of the most recent inst on
123     *  which the given inst depends.  Useful for determining which
124     *  inst must actually be committed before a dependent inst
125     *  can call initiateAcc */
126    InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst,
127        ThreadContext *thread_context);
128
129    /** Can this instruction be issued.  Are any of its source registers
130     *  due to be written by other marked-up instructions in flight */
131    bool canInstIssue(MinorDynInstPtr inst,
132        const std::vector<Cycles> *src_reg_relative_latencies,
133        const std::vector<bool> *cant_forward_from_fu_indices,
134        Cycles now, ThreadContext *thread_context);
135
136    /** MinorTraceIF interface */
137    void minorTrace() const;
138};
139
140}
141
142#endif /* __CPU_MINOR_SCOREBOARD_HH__ */
143