scoreboard.hh revision 10259:ebb376f73dd2
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2013-2014 ARM Limited 36145Snate@binkert.org * All rights reserved 46145Snate@binkert.org * 56145Snate@binkert.org * The license below extends only to copyright in the software and shall 66145Snate@binkert.org * not be construed as granting a license to any other intellectual 76145Snate@binkert.org * property including but not limited to intellectual property relating 86145Snate@binkert.org * to a hardware implementation of the functionality of the software 96145Snate@binkert.org * licensed hereunder. You may use the software subject to the license 106145Snate@binkert.org * terms below provided that you ensure that this notice is replicated 116145Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 126145Snate@binkert.org * modified or unmodified, in source code or in binary form. 136145Snate@binkert.org * 146145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 156145Snate@binkert.org * modification, are permitted provided that the following conditions are 166145Snate@binkert.org * met: redistributions of source code must retain the above copyright 176145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 186145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 196145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 206145Snate@binkert.org * documentation and/or other materials provided with the distribution; 216145Snate@binkert.org * neither the name of the copyright holders nor the names of its 226145Snate@binkert.org * contributors may be used to endorse or promote products derived from 236145Snate@binkert.org * this software without specific prior written permission. 246145Snate@binkert.org * 256145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2911793Sbrandon.potter@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3011793Sbrandon.potter@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110467Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212334Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337056Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347632SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358232Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368232Snate@binkert.org * 378615Snilay@cs.wisc.edu * Authors: Andrew Bardsley 389104Shestness@cs.utexas.edu */ 3911793Sbrandon.potter@amd.com 408615Snilay@cs.wisc.edu/** 418615Snilay@cs.wisc.edu * @file 427039Snate@binkert.org * 438229Snate@binkert.org * A simple instruction scoreboard for tracking dependencies in Execute. 4411108Sdavid.hashe@amd.com */ 4510467Sandreas.hansson@arm.com 466876Ssteve.reinhardt@amd.com#ifndef __CPU_MINOR_SCOREBOARD_HH__ 477055Snate@binkert.org#define __CPU_MINOR_SCOREBOARD_HH__ 487055Snate@binkert.org 496876Ssteve.reinhardt@amd.com#include "cpu/minor/cpu.hh" 506876Ssteve.reinhardt@amd.com#include "cpu/minor/dyn_inst.hh" 516285Snate@binkert.org#include "cpu/minor/trace.hh" 526876Ssteve.reinhardt@amd.com 536285Snate@binkert.orgnamespace Minor 547039Snate@binkert.org{ 556876Ssteve.reinhardt@amd.com 5612133Sspwilson2@wisc.edu/** A scoreboard of register dependencies including, for each register: 5712133Sspwilson2@wisc.edu * The number of in-flight instructions which will generate a result for 586876Ssteve.reinhardt@amd.com * this register */ 596876Ssteve.reinhardt@amd.comclass Scoreboard : public Named 606285Snate@binkert.org{ 616876Ssteve.reinhardt@amd.com public: 626876Ssteve.reinhardt@amd.com /** The number of registers in the Scoreboard. These 6311019Sjthestness@gmail.com * are just the integer, CC and float registers packed 6411019Sjthestness@gmail.com * together with integer regs in the range [0,NumIntRegs-1], 656876Ssteve.reinhardt@amd.com * CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1] 666876Ssteve.reinhardt@amd.com * and float regs in the range 676899SBrad.Beckmann@amd.com * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */ 6811308Santhony.gutierrez@amd.com const unsigned numRegs; 696876Ssteve.reinhardt@amd.com 706876Ssteve.reinhardt@amd.com /** Type to use for thread context registers */ 716876Ssteve.reinhardt@amd.com typedef TheISA::RegIndex RegIndex; 726876Ssteve.reinhardt@amd.com 7311019Sjthestness@gmail.com /** Type to use when indexing numResults */ 7411019Sjthestness@gmail.com typedef unsigned short int Index; 758171Stushar@csail.mit.edu 7611660Stushar@ece.gatech.edu /** Count of the number of in-flight instructions that 776145Snate@binkert.org * have results for each register */ 786145Snate@binkert.org std::vector<Index> numResults; 797039Snate@binkert.org 807039Snate@binkert.org /** Count of the number of results which can't be predicted */ 816145Snate@binkert.org std::vector<Index> numUnpredictableResults; 826145Snate@binkert.org 837039Snate@binkert.org /** Index of the FU generating this result */ 847039Snate@binkert.org std::vector<int> fuIndices; 857039Snate@binkert.org 8610913Sandreas.sandberg@arm.com /** The estimated cycle number that the result will be presented. 879245Shestness@cs.wisc.edu * This can be offset from to allow forwarding to be simulated as 887039Snate@binkert.org * long as instruction completion is *strictly* in order with 899501Snilay@cs.wisc.edu * respect to instructions with unpredictable result timing */ 906145Snate@binkert.org std::vector<Cycles> returnCycle; 917039Snate@binkert.org 927039Snate@binkert.org /** The execute sequence number of the most recent inst to generate this 936285Snate@binkert.org * register value */ 947455Snate@binkert.org std::vector<InstSeqNum> writingInst; 957455Snate@binkert.org 967455Snate@binkert.org public: 977455Snate@binkert.org Scoreboard(const std::string &name) : 987455Snate@binkert.org Named(name), 997455Snate@binkert.org numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs + 1007455Snate@binkert.org TheISA::NumFloatRegs), 1017805Snilay@cs.wisc.edu numResults(numRegs, 0), 10211025Snilay@cs.wisc.edu numUnpredictableResults(numRegs, 0), 10311025Snilay@cs.wisc.edu fuIndices(numRegs, 0), 10411025Snilay@cs.wisc.edu returnCycle(numRegs, Cycles(0)), 1059467Smalek.musleh@gmail.com writingInst(numRegs, 0) 1069467Smalek.musleh@gmail.com { } 1076145Snate@binkert.org 1086145Snate@binkert.org public: 1097455Snate@binkert.org /** Sets scoreboard_index to the index into numResults of the 1107455Snate@binkert.org * given register index. Returns true if the given register 1117455Snate@binkert.org * is in the scoreboard and false if it isn't */ 1127455Snate@binkert.org bool findIndex(RegIndex reg, Index &scoreboard_index); 1137455Snate@binkert.org 1147455Snate@binkert.org /** Mark up an instruction's effects by incrementing 1157455Snate@binkert.org * numResults counts. If mark_unpredictable is true, the inst's 1167805Snilay@cs.wisc.edu * destination registers are marked as being unpredictable without 11711025Snilay@cs.wisc.edu * an estimated retire time */ 11811025Snilay@cs.wisc.edu void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, 11911025Snilay@cs.wisc.edu ThreadContext *thread_context, bool mark_unpredictable); 1209467Smalek.musleh@gmail.com 1219467Smalek.musleh@gmail.com /** Clear down the dependencies for this instruction. clear_unpredictable 1226145Snate@binkert.org * must match mark_unpredictable for the same inst. */ 1236285Snate@binkert.org void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable); 1247039Snate@binkert.org 1257039Snate@binkert.org /** Returns the exec sequence number of the most recent inst on 1266145Snate@binkert.org * which the given inst depends. Useful for determining which 1277039Snate@binkert.org * inst must actually be committed before a dependent inst 1287039Snate@binkert.org * can call initiateAcc */ 1297039Snate@binkert.org InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, 1307039Snate@binkert.org ThreadContext *thread_context); 1319465Snilay@cs.wisc.edu 1327039Snate@binkert.org /** Can this instruction be issued. Are any of its source registers 1336145Snate@binkert.org * due to be written by other marked-up instructions in flight */ 1346145Snate@binkert.org bool canInstIssue(MinorDynInstPtr inst, 13510012Snilay@cs.wisc.edu const std::vector<Cycles> *src_reg_relative_latencies, 1369598Snilay@cs.wisc.edu const std::vector<bool> *cant_forward_from_fu_indices, 13710012Snilay@cs.wisc.edu Cycles now, ThreadContext *thread_context); 13810012Snilay@cs.wisc.edu 13910012Snilay@cs.wisc.edu /** MinorTraceIF interface */ 1409773Snilay@cs.wisc.edu void minorTrace() const; 14110012Snilay@cs.wisc.edu}; 14210012Snilay@cs.wisc.edu 14310012Snilay@cs.wisc.edu} 1449773Snilay@cs.wisc.edu 14510012Snilay@cs.wisc.edu#endif /* __CPU_MINOR_SCOREBOARD_HH__ */ 14610012Snilay@cs.wisc.edu