pipeline.hh revision 11567
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2013-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com/** 4110259SAndrew.Bardsley@arm.com * @file 4210259SAndrew.Bardsley@arm.com * 4310259SAndrew.Bardsley@arm.com * The constructed pipeline. Kept out of MinorCPU to keep the interface 4410259SAndrew.Bardsley@arm.com * between the CPU and its grubby implementation details clean. 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_PIPELINE_HH__ 4810259SAndrew.Bardsley@arm.com#define __CPU_MINOR_PIPELINE_HH__ 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/activity.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/minor/decode.hh" 5310259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5410259SAndrew.Bardsley@arm.com#include "cpu/minor/fetch1.hh" 5510259SAndrew.Bardsley@arm.com#include "cpu/minor/fetch2.hh" 5610259SAndrew.Bardsley@arm.com#include "params/MinorCPU.hh" 5710259SAndrew.Bardsley@arm.com#include "sim/ticked_object.hh" 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comnamespace Minor 6010259SAndrew.Bardsley@arm.com{ 6110259SAndrew.Bardsley@arm.com 6210259SAndrew.Bardsley@arm.com/** 6310259SAndrew.Bardsley@arm.com * @namespace Minor 6410259SAndrew.Bardsley@arm.com * 6510259SAndrew.Bardsley@arm.com * Minor contains all the definitions within the MinorCPU apart from the CPU 6610259SAndrew.Bardsley@arm.com * class itself 6710259SAndrew.Bardsley@arm.com */ 6810259SAndrew.Bardsley@arm.com 6910259SAndrew.Bardsley@arm.com/** The constructed pipeline. Kept out of MinorCPU to keep the interface 7010259SAndrew.Bardsley@arm.com * between the CPU and its grubby implementation details clean. */ 7110259SAndrew.Bardsley@arm.comclass Pipeline : public Ticked 7210259SAndrew.Bardsley@arm.com{ 7310259SAndrew.Bardsley@arm.com protected: 7410259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com /** Allow cycles to be skipped when the pipeline is idle */ 7710259SAndrew.Bardsley@arm.com bool allow_idling; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com Latch<ForwardLineData> f1ToF2; 8010259SAndrew.Bardsley@arm.com Latch<BranchData> f2ToF1; 8110259SAndrew.Bardsley@arm.com Latch<ForwardInstData> f2ToD; 8210259SAndrew.Bardsley@arm.com Latch<ForwardInstData> dToE; 8310259SAndrew.Bardsley@arm.com Latch<BranchData> eToF1; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com Execute execute; 8610259SAndrew.Bardsley@arm.com Decode decode; 8710259SAndrew.Bardsley@arm.com Fetch2 fetch2; 8810259SAndrew.Bardsley@arm.com Fetch1 fetch1; 8910259SAndrew.Bardsley@arm.com 9010259SAndrew.Bardsley@arm.com /** Activity recording for the pipeline. This is access through the CPU 9110259SAndrew.Bardsley@arm.com * by the pipeline stages but belongs to the Pipeline as it is the 9210259SAndrew.Bardsley@arm.com * cleanest place to initialise it */ 9310259SAndrew.Bardsley@arm.com MinorActivityRecorder activityRecorder; 9410259SAndrew.Bardsley@arm.com 9510259SAndrew.Bardsley@arm.com public: 9610259SAndrew.Bardsley@arm.com /** Enumerated ids of the 'stages' for the activity recorder */ 9710259SAndrew.Bardsley@arm.com enum StageId 9810259SAndrew.Bardsley@arm.com { 9910259SAndrew.Bardsley@arm.com /* A stage representing wakeup of the whole processor */ 10010259SAndrew.Bardsley@arm.com CPUStageId = 0, 10110259SAndrew.Bardsley@arm.com /* Real pipeline stages */ 10210259SAndrew.Bardsley@arm.com Fetch1StageId, Fetch2StageId, DecodeStageId, ExecuteStageId, 10310259SAndrew.Bardsley@arm.com Num_StageId /* Stage count */ 10410259SAndrew.Bardsley@arm.com }; 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com /** True after drain is called but draining isn't complete */ 10710259SAndrew.Bardsley@arm.com bool needToSignalDrained; 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com public: 11010259SAndrew.Bardsley@arm.com Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms); 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.com public: 11310259SAndrew.Bardsley@arm.com /** Wake up the Fetch unit. This is needed on thread activation esp. 11410259SAndrew.Bardsley@arm.com * after quiesce wakeup */ 11511567Smitch.hayenga@arm.com void wakeupFetch(ThreadID tid); 11610259SAndrew.Bardsley@arm.com 11710259SAndrew.Bardsley@arm.com /** Try to drain the CPU */ 11810913Sandreas.sandberg@arm.com bool drain(); 11910259SAndrew.Bardsley@arm.com 12010259SAndrew.Bardsley@arm.com void drainResume(); 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com /** Test to see if the CPU is drained */ 12310259SAndrew.Bardsley@arm.com bool isDrained(); 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.com /** A custom evaluate allows report in the right place (between 12610259SAndrew.Bardsley@arm.com * stages and pipeline advance) */ 12711169Sandreas.hansson@arm.com void evaluate() override; 12810259SAndrew.Bardsley@arm.com 12911168Sandreas.hansson@arm.com void countCycles(Cycles delta) override 13010464SAndreas.Sandberg@ARM.com { 13110464SAndreas.Sandberg@ARM.com cpu.ppCycles->notify(delta); 13210464SAndreas.Sandberg@ARM.com } 13310464SAndreas.Sandberg@ARM.com 13410259SAndrew.Bardsley@arm.com void minorTrace() const; 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com /** Functions below here are BaseCPU operations passed on to pipeline 13710259SAndrew.Bardsley@arm.com * stages */ 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.com /** Return the IcachePort belonging to Fetch1 for the CPU */ 14010259SAndrew.Bardsley@arm.com MinorCPU::MinorCPUPort &getInstPort(); 14110259SAndrew.Bardsley@arm.com /** Return the DcachePort belonging to Execute for the CPU */ 14210259SAndrew.Bardsley@arm.com MinorCPU::MinorCPUPort &getDataPort(); 14310259SAndrew.Bardsley@arm.com 14410259SAndrew.Bardsley@arm.com /** To give the activity recorder to the CPU */ 14510259SAndrew.Bardsley@arm.com MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; } 14610259SAndrew.Bardsley@arm.com}; 14710259SAndrew.Bardsley@arm.com 14810259SAndrew.Bardsley@arm.com} 14910259SAndrew.Bardsley@arm.com 15010259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_PIPELINE_HH__ */ 151