fetch2.cc revision 10537:47fe87b0cf97
1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andrew Bardsley 38 */ 39 40#include <string> 41 42#include "arch/decoder.hh" 43#include "arch/utility.hh" 44#include "cpu/minor/fetch2.hh" 45#include "cpu/minor/pipeline.hh" 46#include "cpu/pred/bpred_unit.hh" 47#include "debug/Branch.hh" 48#include "debug/Fetch.hh" 49#include "debug/MinorTrace.hh" 50 51namespace Minor 52{ 53 54Fetch2::Fetch2(const std::string &name, 55 MinorCPU &cpu_, 56 MinorCPUParams ¶ms, 57 Latch<ForwardLineData>::Output inp_, 58 Latch<BranchData>::Output branchInp_, 59 Latch<BranchData>::Input predictionOut_, 60 Latch<ForwardInstData>::Input out_, 61 Reservable &next_stage_input_buffer) : 62 Named(name), 63 cpu(cpu_), 64 inp(inp_), 65 branchInp(branchInp_), 66 predictionOut(predictionOut_), 67 out(out_), 68 nextStageReserve(next_stage_input_buffer), 69 outputWidth(params.decodeInputWidth), 70 processMoreThanOneInput(params.fetch2CycleInput), 71 branchPredictor(*params.branchPred), 72 inputBuffer(name + ".inputBuffer", "lines", params.fetch2InputBufferSize), 73 inputIndex(0), 74 pc(TheISA::PCState(0)), 75 havePC(false), 76 lastStreamSeqNum(InstId::firstStreamSeqNum), 77 fetchSeqNum(InstId::firstFetchSeqNum), 78 expectedStreamSeqNum(InstId::firstStreamSeqNum), 79 predictionSeqNum(InstId::firstPredictionSeqNum), 80 blocked(false) 81{ 82 if (outputWidth < 1) 83 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth); 84 85 if (params.fetch2InputBufferSize < 1) { 86 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name, 87 params.fetch2InputBufferSize); 88 } 89} 90 91const ForwardLineData * 92Fetch2::getInput() 93{ 94 /* Get a line from the inputBuffer to work with */ 95 if (!inputBuffer.empty()) { 96 return &(inputBuffer.front()); 97 } else { 98 return NULL; 99 } 100} 101 102void 103Fetch2::popInput() 104{ 105 if (!inputBuffer.empty()) { 106 inputBuffer.front().freeLine(); 107 inputBuffer.pop(); 108 } 109 110 inputIndex = 0; 111} 112 113void 114Fetch2::dumpAllInput() 115{ 116 DPRINTF(Fetch, "Dumping whole input buffer\n"); 117 while (!inputBuffer.empty()) 118 popInput(); 119 120 inputIndex = 0; 121} 122 123void 124Fetch2::updateBranchPrediction(const BranchData &branch) 125{ 126 MinorDynInstPtr inst = branch.inst; 127 128 /* Don't even consider instructions we didn't try to predict or faults */ 129 if (inst->isFault() || !inst->triedToPredict) 130 return; 131 132 switch (branch.reason) { 133 case BranchData::NoBranch: 134 /* No data to update */ 135 break; 136 case BranchData::Interrupt: 137 /* Never try to predict interrupts */ 138 break; 139 case BranchData::SuspendThread: 140 /* Don't need to act on suspends */ 141 break; 142 case BranchData::WakeupFetch: 143 /* Don't need to act on wakeups, no instruction tied to action. */ 144 break; 145 case BranchData::HaltFetch: 146 /* Don't need to act on fetch wakeup */ 147 break; 148 case BranchData::BranchPrediction: 149 /* Shouldn't happen. Fetch2 is the only source of 150 * BranchPredictions */ 151 break; 152 case BranchData::UnpredictedBranch: 153 /* Unpredicted branch or barrier */ 154 DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst); 155 branchPredictor.squash(inst->id.fetchSeqNum, 156 branch.target, true, inst->id.threadId); 157 break; 158 case BranchData::CorrectlyPredictedBranch: 159 /* Predicted taken, was taken */ 160 DPRINTF(Branch, "Branch predicted correctly inst: %s\n", *inst); 161 branchPredictor.update(inst->id.fetchSeqNum, 162 inst->id.threadId); 163 break; 164 case BranchData::BadlyPredictedBranch: 165 /* Predicted taken, not taken */ 166 DPRINTF(Branch, "Branch mis-predicted inst: %s\n", *inst); 167 branchPredictor.squash(inst->id.fetchSeqNum, 168 branch.target /* Not used */, false, inst->id.threadId); 169 break; 170 case BranchData::BadlyPredictedBranchTarget: 171 /* Predicted taken, was taken but to a different target */ 172 DPRINTF(Branch, "Branch mis-predicted target inst: %s target: %s\n", 173 *inst, branch.target); 174 branchPredictor.squash(inst->id.fetchSeqNum, 175 branch.target, true, inst->id.threadId); 176 break; 177 } 178} 179 180void 181Fetch2::predictBranch(MinorDynInstPtr inst, BranchData &branch) 182{ 183 TheISA::PCState inst_pc = inst->pc; 184 185 assert(!inst->predictedTaken); 186 187 /* Skip non-control/sys call instructions */ 188 if (inst->staticInst->isControl() || 189 inst->staticInst->isSyscall()) 190 { 191 /* Tried to predict */ 192 inst->triedToPredict = true; 193 194 DPRINTF(Branch, "Trying to predict for inst: %s\n", *inst); 195 196 if (branchPredictor.predict(inst->staticInst, 197 inst->id.fetchSeqNum, inst_pc, 198 inst->id.threadId)) 199 { 200 inst->predictedTaken = true; 201 inst->predictedTarget = inst_pc; 202 branch.target = inst_pc; 203 } 204 } else { 205 DPRINTF(Branch, "Not attempting prediction for inst: %s\n", *inst); 206 } 207 208 /* If we predict taken, set branch and update sequence numbers */ 209 if (inst->predictedTaken) { 210 /* Update the predictionSeqNum and remember the streamSeqNum that it 211 * was associated with */ 212 expectedStreamSeqNum = inst->id.streamSeqNum; 213 214 BranchData new_branch = BranchData(BranchData::BranchPrediction, 215 inst->id.streamSeqNum, predictionSeqNum + 1, 216 inst->predictedTarget, inst); 217 218 /* Mark with a new prediction number by the stream number of the 219 * instruction causing the prediction */ 220 predictionSeqNum++; 221 branch = new_branch; 222 223 DPRINTF(Branch, "Branch predicted taken inst: %s target: %s" 224 " new predictionSeqNum: %d\n", 225 *inst, inst->predictedTarget, predictionSeqNum); 226 } 227} 228 229void 230Fetch2::evaluate() 231{ 232 inputBuffer.setTail(*inp.outputWire); 233 ForwardInstData &insts_out = *out.inputWire; 234 BranchData prediction; 235 BranchData &branch_inp = *branchInp.outputWire; 236 237 assert(insts_out.isBubble()); 238 239 blocked = false; 240 241 /* React to branches from Execute to update local branch prediction 242 * structures */ 243 updateBranchPrediction(branch_inp); 244 245 /* If a branch arrives, don't try and do anything about it. Only 246 * react to your own predictions */ 247 if (branch_inp.isStreamChange()) { 248 DPRINTF(Fetch, "Dumping all input as a stream changing branch" 249 " has arrived\n"); 250 dumpAllInput(); 251 havePC = false; 252 } 253 254 /* Even when blocked, clear out input lines with the wrong 255 * prediction sequence number */ 256 { 257 const ForwardLineData *line_in = getInput(); 258 259 while (line_in && 260 expectedStreamSeqNum == line_in->id.streamSeqNum && 261 predictionSeqNum != line_in->id.predictionSeqNum) 262 { 263 DPRINTF(Fetch, "Discarding line %s" 264 " due to predictionSeqNum mismatch (expected: %d)\n", 265 line_in->id, predictionSeqNum); 266 267 popInput(); 268 havePC = false; 269 270 if (processMoreThanOneInput) { 271 DPRINTF(Fetch, "Wrapping\n"); 272 line_in = getInput(); 273 } else { 274 line_in = NULL; 275 } 276 } 277 } 278 279 if (!nextStageReserve.canReserve()) { 280 blocked = true; 281 } else { 282 const ForwardLineData *line_in = getInput(); 283 284 unsigned int output_index = 0; 285 286 /* Pack instructions into the output while we can. This may involve 287 * using more than one input line. Note that lineWidth will be 0 288 * for faulting lines */ 289 while (line_in && 290 (line_in->isFault() || 291 inputIndex < line_in->lineWidth) && /* More input */ 292 output_index < outputWidth && /* More output to fill */ 293 prediction.isBubble() /* No predicted branch */) 294 { 295 ThreadContext *thread = cpu.getContext(line_in->id.threadId); 296 TheISA::Decoder *decoder = thread->getDecoderPtr(); 297 298 /* Discard line due to prediction sequence number being wrong but 299 * without the streamSeqNum number having changed */ 300 bool discard_line = 301 expectedStreamSeqNum == line_in->id.streamSeqNum && 302 predictionSeqNum != line_in->id.predictionSeqNum; 303 304 /* Set the PC if the stream changes. Setting havePC to false in 305 * a previous cycle handles all other change of flow of control 306 * issues */ 307 bool set_pc = lastStreamSeqNum != line_in->id.streamSeqNum; 308 309 if (!discard_line && (!havePC || set_pc)) { 310 /* Set the inputIndex to be the MachInst-aligned offset 311 * from lineBaseAddr of the new PC value */ 312 inputIndex = 313 (line_in->pc.instAddr() & BaseCPU::PCMask) - 314 line_in->lineBaseAddr; 315 DPRINTF(Fetch, "Setting new PC value: %s inputIndex: 0x%x" 316 " lineBaseAddr: 0x%x lineWidth: 0x%x\n", 317 line_in->pc, inputIndex, line_in->lineBaseAddr, 318 line_in->lineWidth); 319 pc = line_in->pc; 320 havePC = true; 321 decoder->reset(); 322 } 323 324 /* The generated instruction. Leave as NULL if no instruction 325 * is to be packed into the output */ 326 MinorDynInstPtr dyn_inst = NULL; 327 328 if (discard_line) { 329 /* Rest of line was from an older prediction in the same 330 * stream */ 331 DPRINTF(Fetch, "Discarding line %s (from inputIndex: %d)" 332 " due to predictionSeqNum mismatch (expected: %d)\n", 333 line_in->id, inputIndex, predictionSeqNum); 334 } else if (line_in->isFault()) { 335 /* Pack a fault as a MinorDynInst with ->fault set */ 336 337 /* Make a new instruction and pick up the line, stream, 338 * prediction, thread ids from the incoming line */ 339 dyn_inst = new MinorDynInst(line_in->id); 340 341 /* Fetch and prediction sequence numbers originate here */ 342 dyn_inst->id.fetchSeqNum = fetchSeqNum; 343 dyn_inst->id.predictionSeqNum = predictionSeqNum; 344 /* To complete the set, test that exec sequence number has 345 * not been set */ 346 assert(dyn_inst->id.execSeqNum == 0); 347 348 dyn_inst->pc = pc; 349 350 /* Pack a faulting instruction but allow other 351 * instructions to be generated. (Fetch2 makes no 352 * immediate judgement about streamSeqNum) */ 353 dyn_inst->fault = line_in->fault; 354 DPRINTF(Fetch, "Fault being passed output_index: " 355 "%d: %s\n", output_index, dyn_inst->fault->name()); 356 } else { 357 uint8_t *line = line_in->line; 358 359 TheISA::MachInst inst_word; 360 /* The instruction is wholly in the line, can just 361 * assign */ 362 inst_word = TheISA::gtoh( 363 *(reinterpret_cast<TheISA::MachInst *> 364 (line + inputIndex))); 365 366 if (!decoder->instReady()) { 367 decoder->moreBytes(pc, 368 line_in->lineBaseAddr + inputIndex, inst_word); 369 DPRINTF(Fetch, "Offering MachInst to decoder" 370 " addr: 0x%x\n", line_in->lineBaseAddr + inputIndex); 371 } 372 373 /* Maybe make the above a loop to accomodate ISAs with 374 * instructions longer than sizeof(MachInst) */ 375 376 if (decoder->instReady()) { 377 /* Make a new instruction and pick up the line, stream, 378 * prediction, thread ids from the incoming line */ 379 dyn_inst = new MinorDynInst(line_in->id); 380 381 /* Fetch and prediction sequence numbers originate here */ 382 dyn_inst->id.fetchSeqNum = fetchSeqNum; 383 dyn_inst->id.predictionSeqNum = predictionSeqNum; 384 /* To complete the set, test that exec sequence number 385 * has not been set */ 386 assert(dyn_inst->id.execSeqNum == 0); 387 388 /* Note that the decoder can update the given PC. 389 * Remember not to assign it until *after* calling 390 * decode */ 391 StaticInstPtr decoded_inst = decoder->decode(pc); 392 dyn_inst->staticInst = decoded_inst; 393 394 dyn_inst->pc = pc; 395 396 DPRINTF(Fetch, "Instruction extracted from line %s" 397 " lineWidth: %d output_index: %d inputIndex: %d" 398 " pc: %s inst: %s\n", 399 line_in->id, 400 line_in->lineWidth, output_index, inputIndex, 401 pc, *dyn_inst); 402 403#if THE_ISA == X86_ISA || THE_ISA == ARM_ISA 404 /* In SE mode, it's possible to branch to a microop when 405 * replaying faults such as page faults (or simply 406 * intra-microcode branches in X86). Unfortunately, 407 * as Minor has micro-op decomposition in a separate 408 * pipeline stage from instruction decomposition, the 409 * following advancePC (which may follow a branch with 410 * microPC() != 0) *must* see a fresh macroop. This 411 * kludge should be improved with an addition to PCState 412 * but I offer it in this form for the moment 413 * 414 * X86 can branch within microops so we need to deal with 415 * the case that, after a branch, the first un-advanced PC 416 * may be pointing to a microop other than 0. Once 417 * advanced, however, the microop number *must* be 0 */ 418 pc.upc(0); 419 pc.nupc(1); 420#endif 421 422 /* Advance PC for the next instruction */ 423 TheISA::advancePC(pc, decoded_inst); 424 425 /* Predict any branches and issue a branch if 426 * necessary */ 427 predictBranch(dyn_inst, prediction); 428 } else { 429 DPRINTF(Fetch, "Inst not ready yet\n"); 430 } 431 432 /* Step on the pointer into the line if there's no 433 * complete instruction waiting */ 434 if (decoder->needMoreBytes()) { 435 inputIndex += sizeof(TheISA::MachInst); 436 437 DPRINTF(Fetch, "Updated inputIndex value PC: %s" 438 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n", 439 line_in->pc, inputIndex, line_in->lineBaseAddr, 440 line_in->lineWidth); 441 } 442 } 443 444 if (dyn_inst) { 445 /* Step to next sequence number */ 446 fetchSeqNum++; 447 448 /* Correctly size the output before writing */ 449 if (output_index == 0) 450 insts_out.resize(outputWidth); 451 /* Pack the generated dynamic instruction into the output */ 452 insts_out.insts[output_index] = dyn_inst; 453 output_index++; 454 455 /* Output MinorTrace instruction info for 456 * pre-microop decomposition macroops */ 457 if (DTRACE(MinorTrace) && !dyn_inst->isFault() && 458 dyn_inst->staticInst->isMacroop()) 459 { 460 dyn_inst->minorTraceInst(*this); 461 } 462 } 463 464 /* Remember the streamSeqNum of this line so we can tell when 465 * we change stream */ 466 lastStreamSeqNum = line_in->id.streamSeqNum; 467 468 /* Asked to discard line or there was a branch or fault */ 469 if (!prediction.isBubble() || /* The remains of a 470 line with a prediction in it */ 471 line_in->isFault() /* A line which is just a fault */) 472 { 473 DPRINTF(Fetch, "Discarding all input on branch/fault\n"); 474 dumpAllInput(); 475 havePC = false; 476 line_in = NULL; 477 } else if (discard_line) { 478 /* Just discard one line, one's behind it may have new 479 * stream sequence numbers. There's a DPRINTF above 480 * for this event */ 481 popInput(); 482 havePC = false; 483 line_in = NULL; 484 } else if (inputIndex == line_in->lineWidth) { 485 /* Got to end of a line, pop the line but keep PC 486 * in case this is a line-wrapping inst. */ 487 popInput(); 488 line_in = NULL; 489 } 490 491 if (!line_in && processMoreThanOneInput) { 492 DPRINTF(Fetch, "Wrapping\n"); 493 line_in = getInput(); 494 } 495 } 496 497 /* The rest of the output (if any) should already have been packed 498 * with bubble instructions by insts_out's initialisation */ 499 } 500 501 /** Reserve a slot in the next stage and output data */ 502 *predictionOut.inputWire = prediction; 503 504 /* If we generated output, reserve space for the result in the next stage 505 * and mark the stage as being active this cycle */ 506 if (!insts_out.isBubble()) { 507 /* Note activity of following buffer */ 508 cpu.activityRecorder->activity(); 509 nextStageReserve.reserve(); 510 } 511 512 /* If we still have input to process and somewhere to put it, 513 * mark stage as active */ 514 if (getInput() && nextStageReserve.canReserve()) 515 cpu.activityRecorder->activateStage(Pipeline::Fetch2StageId); 516 517 /* Make sure the input (if any left) is pushed */ 518 inputBuffer.pushTail(); 519} 520 521bool 522Fetch2::isDrained() 523{ 524 return inputBuffer.empty() && 525 (*inp.outputWire).isBubble() && 526 (*predictionOut.inputWire).isBubble(); 527} 528 529void 530Fetch2::minorTrace() const 531{ 532 std::ostringstream data; 533 534 if (blocked) 535 data << 'B'; 536 else 537 (*out.inputWire).reportData(data); 538 539 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n", 540 inputIndex, havePC, predictionSeqNum, data.str()); 541 inputBuffer.minorTrace(); 542} 543 544} 545