fetch1.hh revision 10713
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2013-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com/** 4110259SAndrew.Bardsley@arm.com * @file 4210259SAndrew.Bardsley@arm.com * 4310259SAndrew.Bardsley@arm.com * Fetch1 is responsible for fetching "lines" from memory and passing 4410259SAndrew.Bardsley@arm.com * them to Fetch2 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_FETCH1_HH__ 4810259SAndrew.Bardsley@arm.com#define __CPU_MINOR_FETCH1_HH__ 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/buffers.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/minor/pipe_data.hh" 5310259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 5410259SAndrew.Bardsley@arm.com#include "mem/packet.hh" 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.comnamespace Minor 5710259SAndrew.Bardsley@arm.com{ 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.com/** A stage responsible for fetching "lines" from memory and passing 6010259SAndrew.Bardsley@arm.com * them to Fetch2 */ 6110259SAndrew.Bardsley@arm.comclass Fetch1 : public Named 6210259SAndrew.Bardsley@arm.com{ 6310259SAndrew.Bardsley@arm.com protected: 6410259SAndrew.Bardsley@arm.com /** Exposable fetch port */ 6510259SAndrew.Bardsley@arm.com class IcachePort : public MinorCPU::MinorCPUPort 6610259SAndrew.Bardsley@arm.com { 6710259SAndrew.Bardsley@arm.com protected: 6810259SAndrew.Bardsley@arm.com /** My owner */ 6910259SAndrew.Bardsley@arm.com Fetch1 &fetch; 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.com public: 7210259SAndrew.Bardsley@arm.com IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : 7310259SAndrew.Bardsley@arm.com MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_) 7410259SAndrew.Bardsley@arm.com { } 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com protected: 7710259SAndrew.Bardsley@arm.com bool recvTimingResp(PacketPtr pkt) 7810259SAndrew.Bardsley@arm.com { return fetch.recvTimingResp(pkt); } 7910259SAndrew.Bardsley@arm.com 8010713Sandreas.hansson@arm.com void recvReqRetry() { fetch.recvReqRetry(); } 8110259SAndrew.Bardsley@arm.com }; 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.com /** Memory access queuing. 8410259SAndrew.Bardsley@arm.com * 8510259SAndrew.Bardsley@arm.com * A request can be submitted by pushing it onto the requests queue after 8610259SAndrew.Bardsley@arm.com * issuing an ITLB lookup (state becomes InTranslation) with a 8710259SAndrew.Bardsley@arm.com * FetchSenderState senderState containing the current lineSeqNum and 8810259SAndrew.Bardsley@arm.com * stream/predictionSeqNum. 8910259SAndrew.Bardsley@arm.com * 9010259SAndrew.Bardsley@arm.com * Translated packets (state becomes Translation) are then passed to the 9110259SAndrew.Bardsley@arm.com * memory system and the transfers queue (state becomes RequestIssuing). 9210259SAndrew.Bardsley@arm.com * Retries are handled by leaving the packet on the requests queue and 9310259SAndrew.Bardsley@arm.com * changing the state to IcacheNeedsRetry). 9410259SAndrew.Bardsley@arm.com * 9510259SAndrew.Bardsley@arm.com * Responses from the memory system alter the request object (state 9610259SAndrew.Bardsley@arm.com * become Complete). Responses can be picked up from the head of the 9710259SAndrew.Bardsley@arm.com * transfers queue to pass on to Fetch2. */ 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.com /** Structure to hold SenderState info through 10010259SAndrew.Bardsley@arm.com * translation and memory accesses. */ 10110259SAndrew.Bardsley@arm.com class FetchRequest : 10210259SAndrew.Bardsley@arm.com public BaseTLB::Translation, /* For TLB lookups */ 10310259SAndrew.Bardsley@arm.com public Packet::SenderState /* For packing into a Packet */ 10410259SAndrew.Bardsley@arm.com { 10510259SAndrew.Bardsley@arm.com protected: 10610259SAndrew.Bardsley@arm.com /** Owning fetch unit */ 10710259SAndrew.Bardsley@arm.com Fetch1 &fetch; 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com public: 11010259SAndrew.Bardsley@arm.com /** Progress of this request through address translation and 11110259SAndrew.Bardsley@arm.com * memory */ 11210259SAndrew.Bardsley@arm.com enum FetchRequestState 11310259SAndrew.Bardsley@arm.com { 11410259SAndrew.Bardsley@arm.com NotIssued, /* Just been made */ 11510259SAndrew.Bardsley@arm.com InTranslation, /* Issued to ITLB, must wait for reqply */ 11610259SAndrew.Bardsley@arm.com Translated, /* Translation complete */ 11710259SAndrew.Bardsley@arm.com RequestIssuing, /* Issued to memory, must wait for response */ 11810259SAndrew.Bardsley@arm.com Complete /* Complete. Either a fault, or a fetched line */ 11910259SAndrew.Bardsley@arm.com }; 12010259SAndrew.Bardsley@arm.com 12110259SAndrew.Bardsley@arm.com FetchRequestState state; 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com /** Identity of the line that this request will generate */ 12410259SAndrew.Bardsley@arm.com InstId id; 12510259SAndrew.Bardsley@arm.com 12610259SAndrew.Bardsley@arm.com /** FetchRequests carry packets while they're in the requests and 12710259SAndrew.Bardsley@arm.com * transfers responses queues. When a Packet returns from the memory 12810259SAndrew.Bardsley@arm.com * system, its request needs to have its packet updated as this may 12910259SAndrew.Bardsley@arm.com * have changed in flight */ 13010259SAndrew.Bardsley@arm.com PacketPtr packet; 13110259SAndrew.Bardsley@arm.com 13210259SAndrew.Bardsley@arm.com /** The underlying request that this fetch represents */ 13310259SAndrew.Bardsley@arm.com Request request; 13410259SAndrew.Bardsley@arm.com 13510259SAndrew.Bardsley@arm.com /** PC to fixup with line address */ 13610259SAndrew.Bardsley@arm.com TheISA::PCState pc; 13710259SAndrew.Bardsley@arm.com 13810259SAndrew.Bardsley@arm.com /** Fill in a fault if one happens during fetch, check this by 13910259SAndrew.Bardsley@arm.com * picking apart the response packet */ 14010259SAndrew.Bardsley@arm.com Fault fault; 14110259SAndrew.Bardsley@arm.com 14210259SAndrew.Bardsley@arm.com /** Make a packet to use with the memory transaction */ 14310259SAndrew.Bardsley@arm.com void makePacket(); 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.com /** Report interface */ 14610259SAndrew.Bardsley@arm.com void reportData(std::ostream &os) const; 14710259SAndrew.Bardsley@arm.com 14810259SAndrew.Bardsley@arm.com /** Is this line out of date with the current stream/prediction 14910259SAndrew.Bardsley@arm.com * sequence and can it be discarded without orphaning in flight 15010259SAndrew.Bardsley@arm.com * TLB lookups/memory accesses? */ 15110259SAndrew.Bardsley@arm.com bool isDiscardable() const; 15210259SAndrew.Bardsley@arm.com 15310259SAndrew.Bardsley@arm.com /** Is this a complete read line or fault */ 15410259SAndrew.Bardsley@arm.com bool isComplete() const { return state == Complete; } 15510259SAndrew.Bardsley@arm.com 15610259SAndrew.Bardsley@arm.com protected: 15710259SAndrew.Bardsley@arm.com /** BaseTLB::Translation interface */ 15810259SAndrew.Bardsley@arm.com 15910259SAndrew.Bardsley@arm.com /** Interface for ITLB responses. We can handle delay, so don't 16010259SAndrew.Bardsley@arm.com * do anything */ 16110259SAndrew.Bardsley@arm.com void markDelayed() { } 16210259SAndrew.Bardsley@arm.com 16310259SAndrew.Bardsley@arm.com /** Interface for ITLB responses. Populates self and then passes 16410259SAndrew.Bardsley@arm.com * the request on to the ports' handleTLBResponse member 16510259SAndrew.Bardsley@arm.com * function */ 16610379Sandreas.hansson@arm.com void finish(const Fault &fault_, RequestPtr request_, 16710379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode); 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.com public: 17010259SAndrew.Bardsley@arm.com FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) : 17110259SAndrew.Bardsley@arm.com SenderState(), 17210259SAndrew.Bardsley@arm.com fetch(fetch_), 17310259SAndrew.Bardsley@arm.com state(NotIssued), 17410259SAndrew.Bardsley@arm.com id(id_), 17510259SAndrew.Bardsley@arm.com packet(NULL), 17610259SAndrew.Bardsley@arm.com request(), 17710259SAndrew.Bardsley@arm.com pc(pc_), 17810259SAndrew.Bardsley@arm.com fault(NoFault) 17910259SAndrew.Bardsley@arm.com { } 18010259SAndrew.Bardsley@arm.com 18110259SAndrew.Bardsley@arm.com ~FetchRequest(); 18210259SAndrew.Bardsley@arm.com }; 18310259SAndrew.Bardsley@arm.com 18410259SAndrew.Bardsley@arm.com typedef FetchRequest *FetchRequestPtr; 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.com protected: 18710259SAndrew.Bardsley@arm.com /** Construction-assigned data members */ 18810259SAndrew.Bardsley@arm.com 18910259SAndrew.Bardsley@arm.com /** Pointer back to the containing CPU */ 19010259SAndrew.Bardsley@arm.com MinorCPU &cpu; 19110259SAndrew.Bardsley@arm.com 19210259SAndrew.Bardsley@arm.com /** Input port carrying branch requests from Execute */ 19310259SAndrew.Bardsley@arm.com Latch<BranchData>::Output inp; 19410259SAndrew.Bardsley@arm.com /** Output port carrying read lines to Fetch2 */ 19510259SAndrew.Bardsley@arm.com Latch<ForwardLineData>::Input out; 19610259SAndrew.Bardsley@arm.com /** Input port carrying branch predictions from Fetch2 */ 19710259SAndrew.Bardsley@arm.com Latch<BranchData>::Output prediction; 19810259SAndrew.Bardsley@arm.com 19910259SAndrew.Bardsley@arm.com /** Interface to reserve space in the next stage */ 20010259SAndrew.Bardsley@arm.com Reservable &nextStageReserve; 20110259SAndrew.Bardsley@arm.com 20210259SAndrew.Bardsley@arm.com /** IcachePort to pass to the CPU. Fetch1 is the only module that uses 20310259SAndrew.Bardsley@arm.com * it. */ 20410259SAndrew.Bardsley@arm.com IcachePort icachePort; 20510259SAndrew.Bardsley@arm.com 20610259SAndrew.Bardsley@arm.com /** Line snap size in bytes. All fetches clip to make their ends not 20710259SAndrew.Bardsley@arm.com * extend beyond this limit. Setting this to the machine L1 cache line 20810259SAndrew.Bardsley@arm.com * length will result in fetches never crossing line boundaries. */ 20910259SAndrew.Bardsley@arm.com unsigned int lineSnap; 21010259SAndrew.Bardsley@arm.com 21110259SAndrew.Bardsley@arm.com /** Maximum fetch width in bytes. Setting this (and lineSnap) to the 21210259SAndrew.Bardsley@arm.com * machine L1 cache line length will result in fetches of whole cache 21310259SAndrew.Bardsley@arm.com * lines. Setting this to sizeof(MachInst) will result it fetches of 21410259SAndrew.Bardsley@arm.com * single instructions (except near the end of lineSnap lines) */ 21510259SAndrew.Bardsley@arm.com unsigned int maxLineWidth; 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.com /** Maximum number of fetches allowed in flight (in queues or memory) */ 21810259SAndrew.Bardsley@arm.com unsigned int fetchLimit; 21910259SAndrew.Bardsley@arm.com 22010259SAndrew.Bardsley@arm.com protected: 22110259SAndrew.Bardsley@arm.com /** Cycle-by-cycle state */ 22210259SAndrew.Bardsley@arm.com 22310259SAndrew.Bardsley@arm.com /** State of memory access for head instruction fetch */ 22410259SAndrew.Bardsley@arm.com enum FetchState 22510259SAndrew.Bardsley@arm.com { 22610259SAndrew.Bardsley@arm.com FetchHalted, /* Not fetching, waiting to be woken by transition 22710259SAndrew.Bardsley@arm.com to FetchWaitingForPC. The PC is not valid in this state */ 22810259SAndrew.Bardsley@arm.com FetchWaitingForPC, /* Not fetching, waiting for stream change. 22910259SAndrew.Bardsley@arm.com This doesn't stop issued fetches from being returned and 23010259SAndrew.Bardsley@arm.com processed or for branches to change the state to Running. */ 23110259SAndrew.Bardsley@arm.com FetchRunning /* Try to fetch, when possible */ 23210259SAndrew.Bardsley@arm.com }; 23310259SAndrew.Bardsley@arm.com 23410259SAndrew.Bardsley@arm.com /** Stage cycle-by-cycle state */ 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com FetchState state; 23710259SAndrew.Bardsley@arm.com 23810259SAndrew.Bardsley@arm.com /** Fetch PC value. This is updated by branches from Execute, branch 23910259SAndrew.Bardsley@arm.com * prediction targets from Fetch2 and by incrementing it as we fetch 24010259SAndrew.Bardsley@arm.com * lines subsequent to those two sources. */ 24110259SAndrew.Bardsley@arm.com TheISA::PCState pc; 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com /** Stream sequence number. This changes on request from Execute and is 24410259SAndrew.Bardsley@arm.com * used to tag instructions by the fetch stream to which they belong. 24510259SAndrew.Bardsley@arm.com * Execute originates new prediction sequence numbers. */ 24610259SAndrew.Bardsley@arm.com InstSeqNum streamSeqNum; 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.com /** Prediction sequence number. This changes when requests from Execute 24910259SAndrew.Bardsley@arm.com * or Fetch2 ask for a change of fetch address and is used to tag lines 25010259SAndrew.Bardsley@arm.com * by the prediction to which they belong. Fetch2 originates 25110259SAndrew.Bardsley@arm.com * prediction sequence numbers. */ 25210259SAndrew.Bardsley@arm.com InstSeqNum predictionSeqNum; 25310259SAndrew.Bardsley@arm.com 25410259SAndrew.Bardsley@arm.com /** Blocked indication for report */ 25510259SAndrew.Bardsley@arm.com bool blocked; 25610259SAndrew.Bardsley@arm.com 25710259SAndrew.Bardsley@arm.com /** State of memory access for head instruction fetch */ 25810259SAndrew.Bardsley@arm.com enum IcacheState 25910259SAndrew.Bardsley@arm.com { 26010259SAndrew.Bardsley@arm.com IcacheRunning, /* Default. Step icache queues when possible */ 26110259SAndrew.Bardsley@arm.com IcacheNeedsRetry /* Request rejected, will be asked to retry */ 26210259SAndrew.Bardsley@arm.com }; 26310259SAndrew.Bardsley@arm.com 26410259SAndrew.Bardsley@arm.com typedef Queue<FetchRequestPtr, 26510259SAndrew.Bardsley@arm.com ReportTraitsPtrAdaptor<FetchRequestPtr>, 26610259SAndrew.Bardsley@arm.com NoBubbleTraits<FetchRequestPtr> > 26710259SAndrew.Bardsley@arm.com FetchQueue; 26810259SAndrew.Bardsley@arm.com 26910259SAndrew.Bardsley@arm.com /** Queue of address translated requests from Fetch1 */ 27010259SAndrew.Bardsley@arm.com FetchQueue requests; 27110259SAndrew.Bardsley@arm.com 27210259SAndrew.Bardsley@arm.com /** Queue of in-memory system requests and responses */ 27310259SAndrew.Bardsley@arm.com FetchQueue transfers; 27410259SAndrew.Bardsley@arm.com 27510259SAndrew.Bardsley@arm.com /** Retry state of icache_port */ 27610259SAndrew.Bardsley@arm.com IcacheState icacheState; 27710259SAndrew.Bardsley@arm.com 27810259SAndrew.Bardsley@arm.com /** Sequence number for line fetch used for ordering lines to flush */ 27910259SAndrew.Bardsley@arm.com InstSeqNum lineSeqNum; 28010259SAndrew.Bardsley@arm.com 28110259SAndrew.Bardsley@arm.com /** Count of the number fetches which have left the transfers queue 28210259SAndrew.Bardsley@arm.com * and are in the 'wild' in the memory system. Try not to rely on 28310259SAndrew.Bardsley@arm.com * this value, it's better to code without knowledge of the number 28410259SAndrew.Bardsley@arm.com * of outstanding accesses */ 28510259SAndrew.Bardsley@arm.com unsigned int numFetchesInMemorySystem; 28610259SAndrew.Bardsley@arm.com /** Number of requests inside the ITLB rather than in the queues. 28710259SAndrew.Bardsley@arm.com * All requests so located *must* have reserved space in the 28810259SAndrew.Bardsley@arm.com * transfers queue */ 28910259SAndrew.Bardsley@arm.com unsigned int numFetchesInITLB; 29010259SAndrew.Bardsley@arm.com 29110259SAndrew.Bardsley@arm.com protected: 29210259SAndrew.Bardsley@arm.com friend std::ostream &operator <<(std::ostream &os, 29310259SAndrew.Bardsley@arm.com Fetch1::FetchState state); 29410259SAndrew.Bardsley@arm.com 29510259SAndrew.Bardsley@arm.com /** Start fetching from a new address. */ 29610259SAndrew.Bardsley@arm.com void changeStream(const BranchData &branch); 29710259SAndrew.Bardsley@arm.com 29810259SAndrew.Bardsley@arm.com /** Update streamSeqNum and predictionSeqNum from the given branch (and 29910259SAndrew.Bardsley@arm.com * assume these have changed and discard (on delivery) all lines in 30010259SAndrew.Bardsley@arm.com * flight) */ 30110259SAndrew.Bardsley@arm.com void updateExpectedSeqNums(const BranchData &branch); 30210259SAndrew.Bardsley@arm.com 30310259SAndrew.Bardsley@arm.com /** Convert a response to a ForwardLineData */ 30410259SAndrew.Bardsley@arm.com void processResponse(FetchRequestPtr response, 30510259SAndrew.Bardsley@arm.com ForwardLineData &line); 30610259SAndrew.Bardsley@arm.com 30710259SAndrew.Bardsley@arm.com friend std::ostream &operator <<(std::ostream &os, 30810259SAndrew.Bardsley@arm.com IcacheState state); 30910259SAndrew.Bardsley@arm.com 31010259SAndrew.Bardsley@arm.com /** Insert a line fetch into the requests. This can be a partial 31110259SAndrew.Bardsley@arm.com * line request where the given address has a non-0 offset into a 31210259SAndrew.Bardsley@arm.com * line. */ 31310259SAndrew.Bardsley@arm.com void fetchLine(); 31410259SAndrew.Bardsley@arm.com 31510259SAndrew.Bardsley@arm.com /** Try and issue a fetch for a translated request at the 31610259SAndrew.Bardsley@arm.com * head of the requests queue. Also tries to move the request 31710259SAndrew.Bardsley@arm.com * between queues */ 31810259SAndrew.Bardsley@arm.com void tryToSendToTransfers(FetchRequestPtr request); 31910259SAndrew.Bardsley@arm.com 32010259SAndrew.Bardsley@arm.com /** Try to send (or resend) a memory request's next/only packet to 32110259SAndrew.Bardsley@arm.com * the memory system. Returns true if the fetch was successfully 32210259SAndrew.Bardsley@arm.com * sent to memory */ 32310259SAndrew.Bardsley@arm.com bool tryToSend(FetchRequestPtr request); 32410259SAndrew.Bardsley@arm.com 32510259SAndrew.Bardsley@arm.com /** Move a request between queues */ 32610259SAndrew.Bardsley@arm.com void moveFromRequestsToTransfers(FetchRequestPtr request); 32710259SAndrew.Bardsley@arm.com 32810259SAndrew.Bardsley@arm.com /** Step requests along between requests and transfers queues */ 32910259SAndrew.Bardsley@arm.com void stepQueues(); 33010259SAndrew.Bardsley@arm.com 33110259SAndrew.Bardsley@arm.com /** Pop a request from the given queue and correctly deallocate and 33210259SAndrew.Bardsley@arm.com * discard it. */ 33310259SAndrew.Bardsley@arm.com void popAndDiscard(FetchQueue &queue); 33410259SAndrew.Bardsley@arm.com 33510259SAndrew.Bardsley@arm.com /** Handle pushing a TLB response onto the right queue */ 33610259SAndrew.Bardsley@arm.com void handleTLBResponse(FetchRequestPtr response); 33710259SAndrew.Bardsley@arm.com 33810259SAndrew.Bardsley@arm.com /** Returns the total number of queue occupancy, in-ITLB and 33910259SAndrew.Bardsley@arm.com * in-memory system fetches */ 34010259SAndrew.Bardsley@arm.com unsigned int numInFlightFetches(); 34110259SAndrew.Bardsley@arm.com 34210259SAndrew.Bardsley@arm.com /** Print the appropriate MinorLine line for a fetch response */ 34310259SAndrew.Bardsley@arm.com void minorTraceResponseLine(const std::string &name, 34410259SAndrew.Bardsley@arm.com FetchRequestPtr response) const; 34510259SAndrew.Bardsley@arm.com 34610259SAndrew.Bardsley@arm.com /** Memory interface */ 34710259SAndrew.Bardsley@arm.com virtual bool recvTimingResp(PacketPtr pkt); 34810713Sandreas.hansson@arm.com virtual void recvReqRetry(); 34910259SAndrew.Bardsley@arm.com 35010259SAndrew.Bardsley@arm.com public: 35110259SAndrew.Bardsley@arm.com Fetch1(const std::string &name_, 35210259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 35310259SAndrew.Bardsley@arm.com MinorCPUParams ¶ms, 35410259SAndrew.Bardsley@arm.com Latch<BranchData>::Output inp_, 35510259SAndrew.Bardsley@arm.com Latch<ForwardLineData>::Input out_, 35610259SAndrew.Bardsley@arm.com Latch<BranchData>::Output prediction_, 35710259SAndrew.Bardsley@arm.com Reservable &next_stage_input_buffer); 35810259SAndrew.Bardsley@arm.com 35910259SAndrew.Bardsley@arm.com public: 36010259SAndrew.Bardsley@arm.com /** Returns the IcachePort owned by this Fetch1 */ 36110259SAndrew.Bardsley@arm.com MinorCPU::MinorCPUPort &getIcachePort() { return icachePort; } 36210259SAndrew.Bardsley@arm.com 36310259SAndrew.Bardsley@arm.com /** Pass on input/buffer data to the output if you can */ 36410259SAndrew.Bardsley@arm.com void evaluate(); 36510259SAndrew.Bardsley@arm.com 36610259SAndrew.Bardsley@arm.com void minorTrace() const; 36710259SAndrew.Bardsley@arm.com 36810259SAndrew.Bardsley@arm.com /** Is this stage drained? For Fetch1, draining is initiated by 36910259SAndrew.Bardsley@arm.com * Execute signalling a branch with the reason HaltFetch */ 37010259SAndrew.Bardsley@arm.com bool isDrained(); 37110259SAndrew.Bardsley@arm.com}; 37210259SAndrew.Bardsley@arm.com 37310259SAndrew.Bardsley@arm.com} 37410259SAndrew.Bardsley@arm.com 37510259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_FETCH1_HH__ */ 376