execute.cc revision 14105:969b4e972b07
1/* 2 * Copyright (c) 2013-2014,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andrew Bardsley 38 */ 39 40#include "cpu/minor/execute.hh" 41 42#include "arch/locked_mem.hh" 43#include "arch/registers.hh" 44#include "arch/utility.hh" 45#include "cpu/minor/cpu.hh" 46#include "cpu/minor/exec_context.hh" 47#include "cpu/minor/fetch1.hh" 48#include "cpu/minor/lsq.hh" 49#include "cpu/op_class.hh" 50#include "debug/Activity.hh" 51#include "debug/Branch.hh" 52#include "debug/Drain.hh" 53#include "debug/MinorExecute.hh" 54#include "debug/MinorInterrupt.hh" 55#include "debug/MinorMem.hh" 56#include "debug/MinorTrace.hh" 57#include "debug/PCEvent.hh" 58 59namespace Minor 60{ 61 62Execute::Execute(const std::string &name_, 63 MinorCPU &cpu_, 64 MinorCPUParams ¶ms, 65 Latch<ForwardInstData>::Output inp_, 66 Latch<BranchData>::Input out_) : 67 Named(name_), 68 inp(inp_), 69 out(out_), 70 cpu(cpu_), 71 issueLimit(params.executeIssueLimit), 72 memoryIssueLimit(params.executeMemoryIssueLimit), 73 commitLimit(params.executeCommitLimit), 74 memoryCommitLimit(params.executeMemoryCommitLimit), 75 processMoreThanOneInput(params.executeCycleInput), 76 fuDescriptions(*params.executeFuncUnits), 77 numFuncUnits(fuDescriptions.funcUnits.size()), 78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit), 79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue), 80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue), 81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1), 82 lsq(name_ + ".lsq", name_ + ".dcache_port", 83 cpu_, *this, 84 params.executeMaxAccessesInMemory, 85 params.executeMemoryWidth, 86 params.executeLSQRequestsQueueSize, 87 params.executeLSQTransfersQueueSize, 88 params.executeLSQStoreBufferSize, 89 params.executeLSQMaxStoreBufferStoresPerCycle), 90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)), 91 interruptPriority(0), 92 issuePriority(0), 93 commitPriority(0) 94{ 95 if (commitLimit < 1) { 96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 97 commitLimit); 98 } 99 100 if (issueLimit < 1) { 101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 102 issueLimit); 103 } 104 105 if (memoryIssueLimit < 1) { 106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_, 107 memoryIssueLimit); 108 } 109 110 if (memoryCommitLimit > commitLimit) { 111 fatal("%s: executeMemoryCommitLimit (%d) must be <=" 112 " executeCommitLimit (%d)\n", 113 name_, memoryCommitLimit, commitLimit); 114 } 115 116 if (params.executeInputBufferSize < 1) { 117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 118 params.executeInputBufferSize); 119 } 120 121 if (params.executeInputBufferSize < 1) { 122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 123 params.executeInputBufferSize); 124 } 125 126 /* This should be large enough to count all the in-FU instructions 127 * which need to be accounted for in the inFlightInsts 128 * queue */ 129 unsigned int total_slots = 0; 130 131 /* Make FUPipelines for each MinorFU */ 132 for (unsigned int i = 0; i < numFuncUnits; i++) { 133 std::ostringstream fu_name; 134 MinorFU *fu_description = fuDescriptions.funcUnits[i]; 135 136 /* Note the total number of instruction slots (for sizing 137 * the inFlightInst queue) and the maximum latency of any FU 138 * (for sizing the activity recorder) */ 139 total_slots += fu_description->opLat; 140 141 fu_name << name_ << ".fu." << i; 142 143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu); 144 145 funcUnits.push_back(fu); 146 } 147 148 /** Check that there is a functional unit for all operation classes */ 149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) { 150 bool found_fu = false; 151 unsigned int fu_index = 0; 152 153 while (fu_index < numFuncUnits && !found_fu) 154 { 155 if (funcUnits[fu_index]->provides( 156 static_cast<OpClass>(op_class))) 157 { 158 found_fu = true; 159 } 160 fu_index++; 161 } 162 163 if (!found_fu) { 164 warn("No functional unit for OpClass %s\n", 165 Enums::OpClassStrings[op_class]); 166 } 167 } 168 169 /* Per-thread structures */ 170 for (ThreadID tid = 0; tid < params.numThreads; tid++) { 171 std::string tid_str = std::to_string(tid); 172 173 /* Input Buffers */ 174 inputBuffer.push_back( 175 InputBuffer<ForwardInstData>( 176 name_ + ".inputBuffer" + tid_str, "insts", 177 params.executeInputBufferSize)); 178 179 /* Scoreboards */ 180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str)); 181 182 /* In-flight instruction records */ 183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst, 184 ReportTraitsAdaptor<QueuedInst> >( 185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots); 186 187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst, 188 ReportTraitsAdaptor<QueuedInst> >( 189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots); 190 } 191} 192 193const ForwardInstData * 194Execute::getInput(ThreadID tid) 195{ 196 /* Get a line from the inputBuffer to work with */ 197 if (!inputBuffer[tid].empty()) { 198 const ForwardInstData &head = inputBuffer[tid].front(); 199 200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front())); 201 } else { 202 return NULL; 203 } 204} 205 206void 207Execute::popInput(ThreadID tid) 208{ 209 if (!inputBuffer[tid].empty()) 210 inputBuffer[tid].pop(); 211 212 executeInfo[tid].inputIndex = 0; 213} 214 215void 216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) 217{ 218 ThreadContext *thread = cpu.getContext(inst->id.threadId); 219 const TheISA::PCState &pc_before = inst->pc; 220 TheISA::PCState target = thread->pcState(); 221 222 /* Force a branch for SerializeAfter/SquashAfter instructions 223 * at the end of micro-op sequence when we're not suspended */ 224 bool force_branch = thread->status() != ThreadContext::Suspended && 225 !inst->isFault() && 226 inst->isLastOpInInst() && 227 (inst->staticInst->isSerializeAfter() || 228 inst->staticInst->isSquashAfter() || 229 inst->staticInst->isIprAccess()); 230 231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n", 232 pc_before, target, (force_branch ? " (forcing)" : "")); 233 234 /* Will we change the PC to something other than the next instruction? */ 235 bool must_branch = pc_before != target || 236 fault != NoFault || 237 force_branch; 238 239 /* The reason for the branch data we're about to generate, set below */ 240 BranchData::Reason reason = BranchData::NoBranch; 241 242 if (fault == NoFault) 243 { 244 TheISA::advancePC(target, inst->staticInst); 245 thread->pcState(target); 246 247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n", 248 pc_before, target); 249 } 250 251 if (inst->predictedTaken && !force_branch) { 252 /* Predicted to branch */ 253 if (!must_branch) { 254 /* No branch was taken, change stream to get us back to the 255 * intended PC value */ 256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but" 257 " none happened inst: %s\n", 258 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 259 260 reason = BranchData::BadlyPredictedBranch; 261 } else if (inst->predictedTarget == target) { 262 /* Branch prediction got the right target, kill the branch and 263 * carry on. 264 * Note that this information to the branch predictor might get 265 * overwritten by a "real" branch during this cycle */ 266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly" 267 " inst: %s\n", 268 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 269 270 reason = BranchData::CorrectlyPredictedBranch; 271 } else { 272 /* Branch prediction got the wrong target */ 273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x" 274 " but got the wrong target (actual: 0x%x) inst: %s\n", 275 inst->pc.instAddr(), inst->predictedTarget.instAddr(), 276 target.instAddr(), *inst); 277 278 reason = BranchData::BadlyPredictedBranchTarget; 279 } 280 } else if (must_branch) { 281 /* Unpredicted branch */ 282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n", 283 inst->pc.instAddr(), target.instAddr(), *inst); 284 285 reason = BranchData::UnpredictedBranch; 286 } else { 287 /* No branch at all */ 288 reason = BranchData::NoBranch; 289 } 290 291 updateBranchData(inst->id.threadId, reason, inst, target, branch); 292} 293 294void 295Execute::updateBranchData( 296 ThreadID tid, 297 BranchData::Reason reason, 298 MinorDynInstPtr inst, const TheISA::PCState &target, 299 BranchData &branch) 300{ 301 if (reason != BranchData::NoBranch) { 302 /* Bump up the stream sequence number on a real branch*/ 303 if (BranchData::isStreamChange(reason)) 304 executeInfo[tid].streamSeqNum++; 305 306 /* Branches (even mis-predictions) don't change the predictionSeqNum, 307 * just the streamSeqNum */ 308 branch = BranchData(reason, tid, 309 executeInfo[tid].streamSeqNum, 310 /* Maintaining predictionSeqNum if there's no inst is just a 311 * courtesy and looks better on minorview */ 312 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum 313 : inst->id.predictionSeqNum), 314 target, inst); 315 316 DPRINTF(Branch, "Branch data signalled: %s\n", branch); 317 } 318} 319 320void 321Execute::handleMemResponse(MinorDynInstPtr inst, 322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) 323{ 324 ThreadID thread_id = inst->id.threadId; 325 ThreadContext *thread = cpu.getContext(thread_id); 326 327 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 328 329 PacketPtr packet = response->packet; 330 331 bool is_load = inst->staticInst->isLoad(); 332 bool is_store = inst->staticInst->isStore(); 333 bool is_atomic = inst->staticInst->isAtomic(); 334 bool is_prefetch = inst->staticInst->isDataPrefetch(); 335 336 /* If true, the trace's predicate value will be taken from the exec 337 * context predicate, otherwise, it will be set to false */ 338 bool use_context_predicate = true; 339 340 if (inst->translationFault != NoFault) { 341 /* Invoke memory faults. */ 342 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n", 343 inst->translationFault->name()); 344 345 if (inst->staticInst->isPrefetch()) { 346 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n", 347 inst->translationFault->name()); 348 349 /* Don't assign to fault */ 350 } else { 351 /* Take the fault raised during the TLB/memory access */ 352 fault = inst->translationFault; 353 354 fault->invoke(thread, inst->staticInst); 355 } 356 } else if (!packet) { 357 DPRINTF(MinorMem, "Completing failed request inst: %s\n", 358 *inst); 359 use_context_predicate = false; 360 if (!context.readMemAccPredicate()) 361 inst->staticInst->completeAcc(nullptr, &context, inst->traceData); 362 } else if (packet->isError()) { 363 DPRINTF(MinorMem, "Trying to commit error response: %s\n", 364 *inst); 365 366 fatal("Received error response packet for inst: %s\n", *inst); 367 } else if (is_store || is_load || is_prefetch || is_atomic) { 368 assert(packet); 369 370 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n", 371 *inst, packet->getAddr(), packet->getSize()); 372 373 if (is_load && packet->getSize() > 0) { 374 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n", 375 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0])); 376 } 377 378 /* Complete the memory access instruction */ 379 fault = inst->staticInst->completeAcc(packet, &context, 380 inst->traceData); 381 382 if (fault != NoFault) { 383 /* Invoke fault created by instruction completion */ 384 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n", 385 fault->name()); 386 fault->invoke(thread, inst->staticInst); 387 } else { 388 /* Stores need to be pushed into the store buffer to finish 389 * them off */ 390 if (response->needsToBeSentToStoreBuffer()) 391 lsq.sendStoreToStoreBuffer(response); 392 } 393 } else { 394 fatal("There should only ever be reads, " 395 "writes or faults at this point\n"); 396 } 397 398 lsq.popResponse(response); 399 400 if (inst->traceData) { 401 inst->traceData->setPredicate((use_context_predicate ? 402 context.readPredicate() : false)); 403 } 404 405 doInstCommitAccounting(inst); 406 407 /* Generate output to account for branches */ 408 tryToBranch(inst, fault, branch); 409} 410 411bool 412Execute::isInterrupted(ThreadID thread_id) const 413{ 414 return cpu.checkInterrupts(cpu.getContext(thread_id)); 415} 416 417bool 418Execute::takeInterrupt(ThreadID thread_id, BranchData &branch) 419{ 420 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n", 421 cpu.getContext(thread_id)->pcState()); 422 423 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt 424 (cpu.getContext(thread_id)); 425 426 if (interrupt != NoFault) { 427 /* The interrupt *must* set pcState */ 428 cpu.getInterruptController(thread_id)->updateIntrInfo 429 (cpu.getContext(thread_id)); 430 interrupt->invoke(cpu.getContext(thread_id)); 431 432 assert(!lsq.accessesInFlight()); 433 434 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n", 435 interrupt->name(), cpu.getContext(thread_id)->pcState()); 436 437 /* Assume that an interrupt *must* cause a branch. Assert this? */ 438 439 updateBranchData(thread_id, BranchData::Interrupt, 440 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(), 441 branch); 442 } 443 444 return interrupt != NoFault; 445} 446 447bool 448Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, 449 bool &passed_predicate, Fault &fault) 450{ 451 bool issued = false; 452 453 /* Set to true if the mem op. is issued and sent to the mem system */ 454 passed_predicate = false; 455 456 if (!lsq.canRequest()) { 457 /* Not acting on instruction yet as the memory 458 * queues are full */ 459 issued = false; 460 } else { 461 ThreadContext *thread = cpu.getContext(inst->id.threadId); 462 TheISA::PCState old_pc = thread->pcState(); 463 464 ExecContext context(cpu, *cpu.threads[inst->id.threadId], 465 *this, inst); 466 467 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst); 468 469 Fault init_fault = inst->staticInst->initiateAcc(&context, 470 inst->traceData); 471 472 if (inst->inLSQ) { 473 if (init_fault != NoFault) { 474 assert(inst->translationFault != NoFault); 475 // Translation faults are dealt with in handleMemResponse() 476 init_fault = NoFault; 477 } else { 478 // If we have a translation fault then it got suppressed by 479 // initateAcc() 480 inst->translationFault = NoFault; 481 } 482 } 483 484 if (init_fault != NoFault) { 485 DPRINTF(MinorExecute, "Fault on memory inst: %s" 486 " initiateAcc: %s\n", *inst, init_fault->name()); 487 fault = init_fault; 488 } else { 489 /* Only set this if the instruction passed its 490 * predicate */ 491 if (!context.readMemAccPredicate()) { 492 DPRINTF(MinorMem, "No memory access for inst: %s\n", *inst); 493 assert(context.readPredicate()); 494 } 495 passed_predicate = context.readPredicate(); 496 497 /* Set predicate in tracing */ 498 if (inst->traceData) 499 inst->traceData->setPredicate(passed_predicate); 500 501 /* If the instruction didn't pass its predicate (and so will not 502 * progress from here) Try to branch to correct and branch 503 * mis-prediction. */ 504 if (!passed_predicate) { 505 /* Leave it up to commit to handle the fault */ 506 lsq.pushFailedRequest(inst); 507 } 508 } 509 510 /* Restore thread PC */ 511 thread->pcState(old_pc); 512 issued = true; 513 } 514 515 return issued; 516} 517 518/** Increment a cyclic buffer index for indices [0, cycle_size-1] */ 519inline unsigned int 520cyclicIndexInc(unsigned int index, unsigned int cycle_size) 521{ 522 unsigned int ret = index + 1; 523 524 if (ret == cycle_size) 525 ret = 0; 526 527 return ret; 528} 529 530/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */ 531inline unsigned int 532cyclicIndexDec(unsigned int index, unsigned int cycle_size) 533{ 534 int ret = index - 1; 535 536 if (ret < 0) 537 ret = cycle_size - 1; 538 539 return ret; 540} 541 542unsigned int 543Execute::issue(ThreadID thread_id) 544{ 545 const ForwardInstData *insts_in = getInput(thread_id); 546 ExecuteThreadInfo &thread = executeInfo[thread_id]; 547 548 /* Early termination if we have no instructions */ 549 if (!insts_in) 550 return 0; 551 552 /* Start from the first FU */ 553 unsigned int fu_index = 0; 554 555 /* Remains true while instructions are still being issued. If any 556 * instruction fails to issue, this is set to false and we exit issue. 557 * This strictly enforces in-order issue. For other issue behaviours, 558 * a more complicated test in the outer while loop below is needed. */ 559 bool issued = true; 560 561 /* Number of insts issues this cycle to check for issueLimit */ 562 unsigned num_insts_issued = 0; 563 564 /* Number of memory ops issues this cycle to check for memoryIssueLimit */ 565 unsigned num_mem_insts_issued = 0; 566 567 /* Number of instructions discarded this cycle in order to enforce a 568 * discardLimit. @todo, add that parameter? */ 569 unsigned num_insts_discarded = 0; 570 571 do { 572 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; 573 Fault fault = inst->fault; 574 bool discarded = false; 575 bool issued_mem_ref = false; 576 577 if (inst->isBubble()) { 578 /* Skip */ 579 issued = true; 580 } else if (cpu.getContext(thread_id)->status() == 581 ThreadContext::Suspended) 582 { 583 DPRINTF(MinorExecute, "Discarding inst: %s from suspended" 584 " thread\n", *inst); 585 586 issued = true; 587 discarded = true; 588 } else if (inst->id.streamSeqNum != thread.streamSeqNum) { 589 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 590 " state was unexpected, expected: %d\n", 591 *inst, thread.streamSeqNum); 592 issued = true; 593 discarded = true; 594 } else { 595 /* Try and issue an instruction into an FU, assume we didn't and 596 * fix that in the loop */ 597 issued = false; 598 599 /* Try FU from 0 each instruction */ 600 fu_index = 0; 601 602 /* Try and issue a single instruction stepping through the 603 * available FUs */ 604 do { 605 FUPipeline *fu = funcUnits[fu_index]; 606 607 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n", 608 *inst, fu_index); 609 610 /* Does the examined fu have the OpClass-related capability 611 * needed to execute this instruction? Faults can always 612 * issue to any FU but probably should just 'live' in the 613 * inFlightInsts queue rather than having an FU. */ 614 bool fu_is_capable = (!inst->isFault() ? 615 fu->provides(inst->staticInst->opClass()) : true); 616 617 if (inst->isNoCostInst()) { 618 /* Issue free insts. to a fake numbered FU */ 619 fu_index = noCostFUIndex; 620 621 /* And start the countdown on activity to allow 622 * this instruction to get to the end of its FU */ 623 cpu.activityRecorder->activity(); 624 625 /* Mark the destinations for this instruction as 626 * busy */ 627 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 628 Cycles(0), cpu.getContext(thread_id), false); 629 630 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex); 631 inst->fuIndex = noCostFUIndex; 632 inst->extraCommitDelay = Cycles(0); 633 inst->extraCommitDelayExpr = NULL; 634 635 /* Push the instruction onto the inFlight queue so 636 * it can be committed in order */ 637 QueuedInst fu_inst(inst); 638 thread.inFlightInsts->push(fu_inst); 639 640 issued = true; 641 642 } else if (!fu_is_capable || fu->alreadyPushed()) { 643 /* Skip */ 644 if (!fu_is_capable) { 645 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't" 646 " capable\n", fu_index); 647 } else { 648 DPRINTF(MinorExecute, "Can't issue as FU: %d is" 649 " already busy\n", fu_index); 650 } 651 } else if (fu->stalled) { 652 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d," 653 " it's stalled\n", 654 *inst, fu_index); 655 } else if (!fu->canInsert()) { 656 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU" 657 " for another: %d cycles\n", 658 *inst, fu->cyclesBeforeInsert()); 659 } else { 660 MinorFUTiming *timing = (!inst->isFault() ? 661 fu->findTiming(inst->staticInst) : NULL); 662 663 const std::vector<Cycles> *src_latencies = 664 (timing ? &(timing->srcRegsRelativeLats) 665 : NULL); 666 667 const std::vector<bool> *cant_forward_from_fu_indices = 668 &(fu->cantForwardFromFUIndices); 669 670 if (timing && timing->suppress) { 671 DPRINTF(MinorExecute, "Can't issue inst: %s as extra" 672 " decoding is suppressing it\n", 673 *inst); 674 } else if (!scoreboard[thread_id].canInstIssue(inst, 675 src_latencies, cant_forward_from_fu_indices, 676 cpu.curCycle(), cpu.getContext(thread_id))) 677 { 678 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n", 679 *inst); 680 } else { 681 /* Can insert the instruction into this FU */ 682 DPRINTF(MinorExecute, "Issuing inst: %s" 683 " into FU %d\n", *inst, 684 fu_index); 685 686 Cycles extra_dest_retire_lat = Cycles(0); 687 TimingExpr *extra_dest_retire_lat_expr = NULL; 688 Cycles extra_assumed_lat = Cycles(0); 689 690 /* Add the extraCommitDelay and extraAssumeLat to 691 * the FU pipeline timings */ 692 if (timing) { 693 extra_dest_retire_lat = 694 timing->extraCommitLat; 695 extra_dest_retire_lat_expr = 696 timing->extraCommitLatExpr; 697 extra_assumed_lat = 698 timing->extraAssumedLat; 699 } 700 701 issued_mem_ref = inst->isMemRef(); 702 703 QueuedInst fu_inst(inst); 704 705 /* Decorate the inst with FU details */ 706 inst->fuIndex = fu_index; 707 inst->extraCommitDelay = extra_dest_retire_lat; 708 inst->extraCommitDelayExpr = 709 extra_dest_retire_lat_expr; 710 711 if (issued_mem_ref) { 712 /* Remember which instruction this memory op 713 * depends on so that initiateAcc can be called 714 * early */ 715 if (allowEarlyMemIssue) { 716 inst->instToWaitFor = 717 scoreboard[thread_id].execSeqNumToWaitFor(inst, 718 cpu.getContext(thread_id)); 719 720 if (lsq.getLastMemBarrier(thread_id) > 721 inst->instToWaitFor) 722 { 723 DPRINTF(MinorExecute, "A barrier will" 724 " cause a delay in mem ref issue of" 725 " inst: %s until after inst" 726 " %d(exec)\n", *inst, 727 lsq.getLastMemBarrier(thread_id)); 728 729 inst->instToWaitFor = 730 lsq.getLastMemBarrier(thread_id); 731 } else { 732 DPRINTF(MinorExecute, "Memory ref inst:" 733 " %s must wait for inst %d(exec)" 734 " before issuing\n", 735 *inst, inst->instToWaitFor); 736 } 737 738 inst->canEarlyIssue = true; 739 } 740 /* Also queue this instruction in the memory ref 741 * queue to ensure in-order issue to the LSQ */ 742 DPRINTF(MinorExecute, "Pushing mem inst: %s\n", 743 *inst); 744 thread.inFUMemInsts->push(fu_inst); 745 } 746 747 /* Issue to FU */ 748 fu->push(fu_inst); 749 /* And start the countdown on activity to allow 750 * this instruction to get to the end of its FU */ 751 cpu.activityRecorder->activity(); 752 753 /* Mark the destinations for this instruction as 754 * busy */ 755 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 756 fu->description.opLat + 757 extra_dest_retire_lat + 758 extra_assumed_lat, 759 cpu.getContext(thread_id), 760 issued_mem_ref && extra_assumed_lat == Cycles(0)); 761 762 /* Push the instruction onto the inFlight queue so 763 * it can be committed in order */ 764 thread.inFlightInsts->push(fu_inst); 765 766 issued = true; 767 } 768 } 769 770 fu_index++; 771 } while (fu_index != numFuncUnits && !issued); 772 773 if (!issued) 774 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst); 775 } 776 777 if (issued) { 778 /* Generate MinorTrace's MinorInst lines. Do this at commit 779 * to allow better instruction annotation? */ 780 if (DTRACE(MinorTrace) && !inst->isBubble()) 781 inst->minorTraceInst(*this); 782 783 /* Mark up barriers in the LSQ */ 784 if (!discarded && inst->isInst() && 785 inst->staticInst->isMemBarrier()) 786 { 787 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst); 788 lsq.issuedMemBarrierInst(inst); 789 } 790 791 if (inst->traceData && setTraceTimeOnIssue) { 792 inst->traceData->setWhen(curTick()); 793 } 794 795 if (issued_mem_ref) 796 num_mem_insts_issued++; 797 798 if (discarded) { 799 num_insts_discarded++; 800 } else if (!inst->isBubble()) { 801 num_insts_issued++; 802 803 if (num_insts_issued == issueLimit) 804 DPRINTF(MinorExecute, "Reached inst issue limit\n"); 805 } 806 807 thread.inputIndex++; 808 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n", 809 thread.inputIndex); 810 } 811 812 /* Got to the end of a line */ 813 if (thread.inputIndex == insts_in->width()) { 814 popInput(thread_id); 815 /* Set insts_in to null to force us to leave the surrounding 816 * loop */ 817 insts_in = NULL; 818 819 if (processMoreThanOneInput) { 820 DPRINTF(MinorExecute, "Wrapping\n"); 821 insts_in = getInput(thread_id); 822 } 823 } 824 } while (insts_in && thread.inputIndex < insts_in->width() && 825 /* We still have instructions */ 826 fu_index != numFuncUnits && /* Not visited all FUs */ 827 issued && /* We've not yet failed to issue an instruction */ 828 num_insts_issued != issueLimit && /* Still allowed to issue */ 829 num_mem_insts_issued != memoryIssueLimit); 830 831 return num_insts_issued; 832} 833 834bool 835Execute::tryPCEvents(ThreadID thread_id) 836{ 837 ThreadContext *thread = cpu.getContext(thread_id); 838 unsigned int num_pc_event_checks = 0; 839 840 /* Handle PC events on instructions */ 841 Addr oldPC; 842 do { 843 oldPC = thread->instAddr(); 844 cpu.system->pcEventQueue.service(thread); 845 num_pc_event_checks++; 846 } while (oldPC != thread->instAddr()); 847 848 if (num_pc_event_checks > 1) { 849 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n", 850 thread->pcState()); 851 } 852 853 return num_pc_event_checks > 1; 854} 855 856void 857Execute::doInstCommitAccounting(MinorDynInstPtr inst) 858{ 859 assert(!inst->isFault()); 860 861 MinorThread *thread = cpu.threads[inst->id.threadId]; 862 863 /* Increment the many and various inst and op counts in the 864 * thread and system */ 865 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop()) 866 { 867 thread->numInst++; 868 thread->numInsts++; 869 cpu.stats.numInsts++; 870 cpu.system->totalNumInsts++; 871 872 /* Act on events related to instruction counts */ 873 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst); 874 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts); 875 } 876 thread->numOp++; 877 thread->numOps++; 878 cpu.stats.numOps++; 879 cpu.stats.committedInstType[inst->id.threadId] 880 [inst->staticInst->opClass()]++; 881 882 /* Set the CP SeqNum to the numOps commit number */ 883 if (inst->traceData) 884 inst->traceData->setCPSeq(thread->numOp); 885 886 cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr()); 887} 888 889bool 890Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue, 891 BranchData &branch, Fault &fault, bool &committed, 892 bool &completed_mem_issue) 893{ 894 ThreadID thread_id = inst->id.threadId; 895 ThreadContext *thread = cpu.getContext(thread_id); 896 897 bool completed_inst = true; 898 fault = NoFault; 899 900 /* Is the thread for this instruction suspended? In that case, just 901 * stall as long as there are no pending interrupts */ 902 if (thread->status() == ThreadContext::Suspended && 903 !isInterrupted(thread_id)) 904 { 905 panic("We should never hit the case where we try to commit from a " 906 "suspended thread as the streamSeqNum should not match"); 907 } else if (inst->isFault()) { 908 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 909 910 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n", 911 inst->fault->name()); 912 913 fault = inst->fault; 914 inst->fault->invoke(thread, NULL); 915 916 tryToBranch(inst, fault, branch); 917 } else if (inst->staticInst->isMemRef()) { 918 /* Memory accesses are executed in two parts: 919 * executeMemRefInst -- calculates the EA and issues the access 920 * to memory. This is done here. 921 * handleMemResponse -- handles the response packet, done by 922 * Execute::commit 923 * 924 * While the memory access is in its FU, the EA is being 925 * calculated. At the end of the FU, when it is ready to 926 * 'commit' (in this function), the access is presented to the 927 * memory queues. When a response comes back from memory, 928 * Execute::commit will commit it. 929 */ 930 bool predicate_passed = false; 931 bool completed_mem_inst = executeMemRefInst(inst, branch, 932 predicate_passed, fault); 933 934 if (completed_mem_inst && fault != NoFault) { 935 if (early_memory_issue) { 936 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n", 937 fault->name()); 938 /* Don't execute the fault, just stall the instruction 939 * until it gets to the head of inFlightInsts */ 940 inst->canEarlyIssue = false; 941 /* Not completed as we'll come here again to pick up 942 * the fault when we get to the end of the FU */ 943 completed_inst = false; 944 } else { 945 DPRINTF(MinorExecute, "Fault in execute: %s\n", 946 fault->name()); 947 fault->invoke(thread, NULL); 948 949 tryToBranch(inst, fault, branch); 950 completed_inst = true; 951 } 952 } else { 953 completed_inst = completed_mem_inst; 954 } 955 completed_mem_issue = completed_inst; 956 } else if (inst->isInst() && inst->staticInst->isMemBarrier() && 957 !lsq.canPushIntoStoreBuffer()) 958 { 959 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as" 960 " there isn't space in the store buffer\n", *inst); 961 962 completed_inst = false; 963 } else if (inst->isInst() && inst->staticInst->isQuiesce() 964 && !branch.isBubble()){ 965 /* This instruction can suspend, need to be able to communicate 966 * backwards, so no other branches may evaluate this cycle*/ 967 completed_inst = false; 968 } else { 969 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 970 971 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst); 972 973 fault = inst->staticInst->execute(&context, 974 inst->traceData); 975 976 /* Set the predicate for tracing and dump */ 977 if (inst->traceData) 978 inst->traceData->setPredicate(context.readPredicate()); 979 980 committed = true; 981 982 if (fault != NoFault) { 983 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n", 984 *inst, fault->name()); 985 fault->invoke(thread, inst->staticInst); 986 } 987 988 doInstCommitAccounting(inst); 989 tryToBranch(inst, fault, branch); 990 } 991 992 if (completed_inst) { 993 /* Keep a copy of this instruction's predictionSeqNum just in case 994 * we need to issue a branch without an instruction (such as an 995 * interrupt) */ 996 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum; 997 998 /* Check to see if this instruction suspended the current thread. */ 999 if (!inst->isFault() && 1000 thread->status() == ThreadContext::Suspended && 1001 branch.isBubble() && /* It didn't branch too */ 1002 !isInterrupted(thread_id)) /* Don't suspend if we have 1003 interrupts */ 1004 { 1005 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState(); 1006 1007 assert(resume_pc.microPC() == 0); 1008 1009 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute" 1010 " inst: %s\n", thread_id, *inst); 1011 1012 cpu.stats.numFetchSuspends++; 1013 1014 updateBranchData(thread_id, BranchData::SuspendThread, inst, 1015 resume_pc, branch); 1016 } 1017 } 1018 1019 return completed_inst; 1020} 1021 1022void 1023Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, 1024 BranchData &branch) 1025{ 1026 Fault fault = NoFault; 1027 Cycles now = cpu.curCycle(); 1028 ExecuteThreadInfo &ex_info = executeInfo[thread_id]; 1029 1030 /** 1031 * Try and execute as many instructions from the end of FU pipelines as 1032 * possible. This *doesn't* include actually advancing the pipelines. 1033 * 1034 * We do this by looping on the front of the inFlightInsts queue for as 1035 * long as we can find the desired instruction at the end of the 1036 * functional unit it was issued to without seeing a branch or a fault. 1037 * In this function, these terms are used: 1038 * complete -- The instruction has finished its passage through 1039 * its functional unit and its fate has been decided 1040 * (committed, discarded, issued to the memory system) 1041 * commit -- The instruction is complete(d), not discarded and has 1042 * its effects applied to the CPU state 1043 * discard(ed) -- The instruction is complete but not committed 1044 * as its streamSeqNum disagrees with the current 1045 * Execute::streamSeqNum 1046 * 1047 * Commits are also possible from two other places: 1048 * 1049 * 1) Responses returning from the LSQ 1050 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier 1051 * than their position in the inFlightInsts queue, but after all 1052 * their dependencies are resolved. 1053 */ 1054 1055 /* Has an instruction been completed? Once this becomes false, we stop 1056 * trying to complete instructions. */ 1057 bool completed_inst = true; 1058 1059 /* Number of insts committed this cycle to check against commitLimit */ 1060 unsigned int num_insts_committed = 0; 1061 1062 /* Number of memory access instructions committed to check against 1063 * memCommitLimit */ 1064 unsigned int num_mem_refs_committed = 0; 1065 1066 if (only_commit_microops && !ex_info.inFlightInsts->empty()) { 1067 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n", 1068 *(ex_info.inFlightInsts->front().inst), 1069 ex_info.lastCommitWasEndOfMacroop); 1070 } 1071 1072 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */ 1073 !branch.isStreamChange() && /* No real branch */ 1074 fault == NoFault && /* No faults */ 1075 completed_inst && /* Still finding instructions to execute */ 1076 num_insts_committed != commitLimit /* Not reached commit limit */ 1077 ) 1078 { 1079 if (only_commit_microops) { 1080 DPRINTF(MinorInterrupt, "Committing tail of insts before" 1081 " interrupt: %s\n", 1082 *(ex_info.inFlightInsts->front().inst)); 1083 } 1084 1085 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1086 1087 InstSeqNum head_exec_seq_num = 1088 head_inflight_inst->inst->id.execSeqNum; 1089 1090 /* The instruction we actually process if completed_inst 1091 * remains true to the end of the loop body. 1092 * Start by considering the the head of the in flight insts queue */ 1093 MinorDynInstPtr inst = head_inflight_inst->inst; 1094 1095 bool committed_inst = false; 1096 bool discard_inst = false; 1097 bool completed_mem_ref = false; 1098 bool issued_mem_ref = false; 1099 bool early_memory_issue = false; 1100 1101 /* Must set this again to go around the loop */ 1102 completed_inst = false; 1103 1104 /* If we're just completing a macroop before an interrupt or drain, 1105 * can we stil commit another microop (rather than a memory response) 1106 * without crosing into the next full instruction? */ 1107 bool can_commit_insts = !ex_info.inFlightInsts->empty() && 1108 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop); 1109 1110 /* Can we find a mem response for this inst */ 1111 LSQ::LSQRequestPtr mem_response = 1112 (inst->inLSQ ? lsq.findResponse(inst) : NULL); 1113 1114 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n", 1115 can_commit_insts); 1116 1117 /* Test for PC events after every instruction */ 1118 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) { 1119 ThreadContext *thread = cpu.getContext(thread_id); 1120 1121 /* Branch as there was a change in PC */ 1122 updateBranchData(thread_id, BranchData::UnpredictedBranch, 1123 MinorDynInst::bubble(), thread->pcState(), branch); 1124 } else if (mem_response && 1125 num_mem_refs_committed < memoryCommitLimit) 1126 { 1127 /* Try to commit from the memory responses next */ 1128 discard_inst = inst->id.streamSeqNum != 1129 ex_info.streamSeqNum || discard; 1130 1131 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n", 1132 *inst); 1133 1134 /* Complete or discard the response */ 1135 if (discard_inst) { 1136 DPRINTF(MinorExecute, "Discarding mem inst: %s as its" 1137 " stream state was unexpected, expected: %d\n", 1138 *inst, ex_info.streamSeqNum); 1139 1140 lsq.popResponse(mem_response); 1141 } else { 1142 handleMemResponse(inst, mem_response, branch, fault); 1143 committed_inst = true; 1144 } 1145 1146 completed_mem_ref = true; 1147 completed_inst = true; 1148 } else if (can_commit_insts) { 1149 /* If true, this instruction will, subject to timing tweaks, 1150 * be considered for completion. try_to_commit flattens 1151 * the `if' tree a bit and allows other tests for inst 1152 * commit to be inserted here. */ 1153 bool try_to_commit = false; 1154 1155 /* Try and issue memory ops early if they: 1156 * - Can push a request into the LSQ 1157 * - Have reached the end of their FUs 1158 * - Have had all their dependencies satisfied 1159 * - Are from the right stream 1160 * 1161 * For any other case, leave it to the normal instruction 1162 * issue below to handle them. 1163 */ 1164 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1165 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n"); 1166 1167 const MinorDynInstPtr head_mem_ref_inst = 1168 ex_info.inFUMemInsts->front().inst; 1169 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1170 const MinorDynInstPtr &fu_inst = fu->front().inst; 1171 1172 /* Use this, possibly out of order, inst as the one 1173 * to 'commit'/send to the LSQ */ 1174 if (!fu_inst->isBubble() && 1175 !fu_inst->inLSQ && 1176 fu_inst->canEarlyIssue && 1177 ex_info.streamSeqNum == fu_inst->id.streamSeqNum && 1178 head_exec_seq_num > fu_inst->instToWaitFor) 1179 { 1180 DPRINTF(MinorExecute, "Issuing mem ref early" 1181 " inst: %s instToWaitFor: %d\n", 1182 *(fu_inst), fu_inst->instToWaitFor); 1183 1184 inst = fu_inst; 1185 try_to_commit = true; 1186 early_memory_issue = true; 1187 completed_inst = true; 1188 } 1189 } 1190 1191 /* Try and commit FU-less insts */ 1192 if (!completed_inst && inst->isNoCostInst()) { 1193 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst); 1194 1195 try_to_commit = true; 1196 completed_inst = true; 1197 } 1198 1199 /* Try to issue from the ends of FUs and the inFlightInsts 1200 * queue */ 1201 if (!completed_inst && !inst->inLSQ) { 1202 DPRINTF(MinorExecute, "Trying to commit from FUs\n"); 1203 1204 /* Try to commit from a functional unit */ 1205 /* Is the head inst of the expected inst's FU actually the 1206 * expected inst? */ 1207 QueuedInst &fu_inst = 1208 funcUnits[inst->fuIndex]->front(); 1209 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum; 1210 1211 if (fu_inst.inst->isBubble()) { 1212 /* No instruction ready */ 1213 completed_inst = false; 1214 } else if (fu_inst_seq_num != head_exec_seq_num) { 1215 /* Past instruction: we must have already executed it 1216 * in the same cycle and so the head inst isn't 1217 * actually at the end of its pipeline 1218 * Future instruction: handled above and only for 1219 * mem refs on their way to the LSQ */ 1220 } else if (fu_inst.inst->id == inst->id) { 1221 /* All instructions can be committed if they have the 1222 * right execSeqNum and there are no in-flight 1223 * mem insts before us */ 1224 try_to_commit = true; 1225 completed_inst = true; 1226 } 1227 } 1228 1229 if (try_to_commit) { 1230 discard_inst = inst->id.streamSeqNum != 1231 ex_info.streamSeqNum || discard; 1232 1233 /* Is this instruction discardable as its streamSeqNum 1234 * doesn't match? */ 1235 if (!discard_inst) { 1236 /* Try to commit or discard a non-memory instruction. 1237 * Memory ops are actually 'committed' from this FUs 1238 * and 'issued' into the memory system so we need to 1239 * account for them later (commit_was_mem_issue gets 1240 * set) */ 1241 if (inst->extraCommitDelayExpr) { 1242 DPRINTF(MinorExecute, "Evaluating expression for" 1243 " extra commit delay inst: %s\n", *inst); 1244 1245 ThreadContext *thread = cpu.getContext(thread_id); 1246 1247 TimingExprEvalContext context(inst->staticInst, 1248 thread, NULL); 1249 1250 uint64_t extra_delay = inst->extraCommitDelayExpr-> 1251 eval(context); 1252 1253 DPRINTF(MinorExecute, "Extra commit delay expr" 1254 " result: %d\n", extra_delay); 1255 1256 if (extra_delay < 128) { 1257 inst->extraCommitDelay += Cycles(extra_delay); 1258 } else { 1259 DPRINTF(MinorExecute, "Extra commit delay was" 1260 " very long: %d\n", extra_delay); 1261 } 1262 inst->extraCommitDelayExpr = NULL; 1263 } 1264 1265 /* Move the extraCommitDelay from the instruction 1266 * into the minimumCommitCycle */ 1267 if (inst->extraCommitDelay != Cycles(0)) { 1268 inst->minimumCommitCycle = cpu.curCycle() + 1269 inst->extraCommitDelay; 1270 inst->extraCommitDelay = Cycles(0); 1271 } 1272 1273 /* @todo Think about making lastMemBarrier be 1274 * MAX_UINT_64 to avoid using 0 as a marker value */ 1275 if (!inst->isFault() && inst->isMemRef() && 1276 lsq.getLastMemBarrier(thread_id) < 1277 inst->id.execSeqNum && 1278 lsq.getLastMemBarrier(thread_id) != 0) 1279 { 1280 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1281 " as there are incomplete barriers in flight\n", 1282 *inst); 1283 completed_inst = false; 1284 } else if (inst->minimumCommitCycle > now) { 1285 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1286 " as it wants to be stalled for %d more cycles\n", 1287 *inst, inst->minimumCommitCycle - now); 1288 completed_inst = false; 1289 } else { 1290 completed_inst = commitInst(inst, 1291 early_memory_issue, branch, fault, 1292 committed_inst, issued_mem_ref); 1293 } 1294 } else { 1295 /* Discard instruction */ 1296 completed_inst = true; 1297 } 1298 1299 if (completed_inst) { 1300 /* Allow the pipeline to advance. If the FU head 1301 * instruction wasn't the inFlightInsts head 1302 * but had already been committed, it would have 1303 * unstalled the pipeline before here */ 1304 if (inst->fuIndex != noCostFUIndex) { 1305 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id); 1306 funcUnits[inst->fuIndex]->stalled = false; 1307 } 1308 } 1309 } 1310 } else { 1311 DPRINTF(MinorExecute, "No instructions to commit\n"); 1312 completed_inst = false; 1313 } 1314 1315 /* All discardable instructions must also be 'completed' by now */ 1316 assert(!(discard_inst && !completed_inst)); 1317 1318 /* Instruction committed but was discarded due to streamSeqNum 1319 * mismatch */ 1320 if (discard_inst) { 1321 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 1322 " state was unexpected, expected: %d\n", 1323 *inst, ex_info.streamSeqNum); 1324 1325 if (fault == NoFault) 1326 cpu.stats.numDiscardedOps++; 1327 } 1328 1329 /* Mark the mem inst as being in the LSQ */ 1330 if (issued_mem_ref) { 1331 inst->fuIndex = 0; 1332 inst->inLSQ = true; 1333 } 1334 1335 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts 1336 * as they've *definitely* exited the FUs */ 1337 if (completed_inst && inst->isMemRef()) { 1338 /* The MemRef could have been discarded from the FU or the memory 1339 * queue, so just check an FU instruction */ 1340 if (!ex_info.inFUMemInsts->empty() && 1341 ex_info.inFUMemInsts->front().inst == inst) 1342 { 1343 ex_info.inFUMemInsts->pop(); 1344 } 1345 } 1346 1347 if (completed_inst && !(issued_mem_ref && fault == NoFault)) { 1348 /* Note that this includes discarded insts */ 1349 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst); 1350 1351 /* Got to the end of a full instruction? */ 1352 ex_info.lastCommitWasEndOfMacroop = inst->isFault() || 1353 inst->isLastOpInInst(); 1354 1355 /* lastPredictionSeqNum is kept as a convenience to prevent its 1356 * value from changing too much on the minorview display */ 1357 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum; 1358 1359 /* Finished with the inst, remove it from the inst queue and 1360 * clear its dependencies */ 1361 ex_info.inFlightInsts->pop(); 1362 1363 /* Complete barriers in the LSQ/move to store buffer */ 1364 if (inst->isInst() && inst->staticInst->isMemBarrier()) { 1365 DPRINTF(MinorMem, "Completing memory barrier" 1366 " inst: %s committed: %d\n", *inst, committed_inst); 1367 lsq.completeMemBarrierInst(inst, committed_inst); 1368 } 1369 1370 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef()); 1371 } 1372 1373 /* Handle per-cycle instruction counting */ 1374 if (committed_inst) { 1375 bool is_no_cost_inst = inst->isNoCostInst(); 1376 1377 /* Don't show no cost instructions as having taken a commit 1378 * slot */ 1379 if (DTRACE(MinorTrace) && !is_no_cost_inst) 1380 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst; 1381 1382 if (!is_no_cost_inst) 1383 num_insts_committed++; 1384 1385 if (num_insts_committed == commitLimit) 1386 DPRINTF(MinorExecute, "Reached inst commit limit\n"); 1387 1388 /* Re-set the time of the instruction if that's required for 1389 * tracing */ 1390 if (inst->traceData) { 1391 if (setTraceTimeOnCommit) 1392 inst->traceData->setWhen(curTick()); 1393 inst->traceData->dump(); 1394 } 1395 1396 if (completed_mem_ref) 1397 num_mem_refs_committed++; 1398 1399 if (num_mem_refs_committed == memoryCommitLimit) 1400 DPRINTF(MinorExecute, "Reached mem ref commit limit\n"); 1401 } 1402 } 1403} 1404 1405bool 1406Execute::isInbetweenInsts(ThreadID thread_id) const 1407{ 1408 return executeInfo[thread_id].lastCommitWasEndOfMacroop && 1409 !lsq.accessesInFlight(); 1410} 1411 1412void 1413Execute::evaluate() 1414{ 1415 if (!inp.outputWire->isBubble()) 1416 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire); 1417 1418 BranchData &branch = *out.inputWire; 1419 1420 unsigned int num_issued = 0; 1421 1422 /* Do all the cycle-wise activities for dcachePort here to potentially 1423 * free up input spaces in the LSQ's requests queue */ 1424 lsq.step(); 1425 1426 /* Check interrupts first. Will halt commit if interrupt found */ 1427 bool interrupted = false; 1428 ThreadID interrupt_tid = checkInterrupts(branch, interrupted); 1429 1430 if (interrupt_tid != InvalidThreadID) { 1431 /* Signalling an interrupt this cycle, not issuing/committing from 1432 * any other threads */ 1433 } else if (!branch.isBubble()) { 1434 /* It's important that this is here to carry Fetch1 wakeups to Fetch1 1435 * without overwriting them */ 1436 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old" 1437 " branch to complete\n"); 1438 } else { 1439 ThreadID commit_tid = getCommittingThread(); 1440 1441 if (commit_tid != InvalidThreadID) { 1442 ExecuteThreadInfo& commit_info = executeInfo[commit_tid]; 1443 1444 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n", 1445 commit_tid); 1446 /* commit can set stalled flags observable to issue and so *must* be 1447 * called first */ 1448 if (commit_info.drainState != NotDraining) { 1449 if (commit_info.drainState == DrainCurrentInst) { 1450 /* Commit only micro-ops, don't kill anything else */ 1451 commit(commit_tid, true, false, branch); 1452 1453 if (isInbetweenInsts(commit_tid)) 1454 setDrainState(commit_tid, DrainHaltFetch); 1455 1456 /* Discard any generated branch */ 1457 branch = BranchData::bubble(); 1458 } else if (commit_info.drainState == DrainAllInsts) { 1459 /* Kill all instructions */ 1460 while (getInput(commit_tid)) 1461 popInput(commit_tid); 1462 commit(commit_tid, false, true, branch); 1463 } 1464 } else { 1465 /* Commit micro-ops only if interrupted. Otherwise, commit 1466 * anything you like */ 1467 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n", 1468 commit_tid); 1469 bool only_commit_microops = interrupted && 1470 hasInterrupt(commit_tid); 1471 commit(commit_tid, only_commit_microops, false, branch); 1472 } 1473 1474 /* Halt fetch, but don't do it until we have the current instruction in 1475 * the bag */ 1476 if (commit_info.drainState == DrainHaltFetch) { 1477 updateBranchData(commit_tid, BranchData::HaltFetch, 1478 MinorDynInst::bubble(), TheISA::PCState(0), branch); 1479 1480 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1481 setDrainState(commit_tid, DrainAllInsts); 1482 } 1483 } 1484 ThreadID issue_tid = getIssuingThread(); 1485 /* This will issue merrily even when interrupted in the sure and 1486 * certain knowledge that the interrupt with change the stream */ 1487 if (issue_tid != InvalidThreadID) { 1488 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n", 1489 issue_tid); 1490 num_issued = issue(issue_tid); 1491 } 1492 1493 } 1494 1495 /* Run logic to step functional units + decide if we are active on the next 1496 * clock cycle */ 1497 std::vector<MinorDynInstPtr> next_issuable_insts; 1498 bool can_issue_next = false; 1499 1500 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1501 /* Find the next issuable instruction for each thread and see if it can 1502 be issued */ 1503 if (getInput(tid)) { 1504 unsigned int input_index = executeInfo[tid].inputIndex; 1505 MinorDynInstPtr inst = getInput(tid)->insts[input_index]; 1506 if (inst->isFault()) { 1507 can_issue_next = true; 1508 } else if (!inst->isBubble()) { 1509 next_issuable_insts.push_back(inst); 1510 } 1511 } 1512 } 1513 1514 bool becoming_stalled = true; 1515 1516 /* Advance the pipelines and note whether they still need to be 1517 * advanced */ 1518 for (unsigned int i = 0; i < numFuncUnits; i++) { 1519 FUPipeline *fu = funcUnits[i]; 1520 fu->advance(); 1521 1522 /* If we need to tick again, the pipeline will have been left or set 1523 * to be unstalled */ 1524 if (fu->occupancy !=0 && !fu->stalled) 1525 becoming_stalled = false; 1526 1527 /* Could we possibly issue the next instruction from any thread? 1528 * This is quite an expensive test and is only used to determine 1529 * if the CPU should remain active, only run it if we aren't sure 1530 * we are active next cycle yet */ 1531 for (auto inst : next_issuable_insts) { 1532 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) && 1533 scoreboard[inst->id.threadId].canInstIssue(inst, 1534 NULL, NULL, cpu.curCycle() + Cycles(1), 1535 cpu.getContext(inst->id.threadId))) { 1536 can_issue_next = true; 1537 break; 1538 } 1539 } 1540 } 1541 1542 bool head_inst_might_commit = false; 1543 1544 /* Could the head in flight insts be committed */ 1545 for (auto const &info : executeInfo) { 1546 if (!info.inFlightInsts->empty()) { 1547 const QueuedInst &head_inst = info.inFlightInsts->front(); 1548 1549 if (head_inst.inst->isNoCostInst()) { 1550 head_inst_might_commit = true; 1551 } else { 1552 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex]; 1553 if ((fu->stalled && 1554 fu->front().inst->id == head_inst.inst->id) || 1555 lsq.findResponse(head_inst.inst)) 1556 { 1557 head_inst_might_commit = true; 1558 break; 1559 } 1560 } 1561 } 1562 } 1563 1564 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n", 1565 (num_issued != 0 ? " (issued some insts)" : ""), 1566 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"), 1567 (can_issue_next ? " (can issued next inst)" : ""), 1568 (head_inst_might_commit ? "(head inst might commit)" : ""), 1569 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""), 1570 (interrupted ? " (interrupted)" : "")); 1571 1572 bool need_to_tick = 1573 num_issued != 0 || /* Issued some insts this cycle */ 1574 !becoming_stalled || /* Some FU pipelines can still move */ 1575 can_issue_next || /* Can still issue a new inst */ 1576 head_inst_might_commit || /* Could possible commit the next inst */ 1577 lsq.needsToTick() || /* Must step the dcache port */ 1578 interrupted; /* There are pending interrupts */ 1579 1580 if (!need_to_tick) { 1581 DPRINTF(Activity, "The next cycle might be skippable as there are no" 1582 " advanceable FUs\n"); 1583 } 1584 1585 /* Wake up if we need to tick again */ 1586 if (need_to_tick) 1587 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1588 1589 /* Note activity of following buffer */ 1590 if (!branch.isBubble()) 1591 cpu.activityRecorder->activity(); 1592 1593 /* Make sure the input (if any left) is pushed */ 1594 if (!inp.outputWire->isBubble()) 1595 inputBuffer[inp.outputWire->threadId].pushTail(); 1596} 1597 1598ThreadID 1599Execute::checkInterrupts(BranchData& branch, bool& interrupted) 1600{ 1601 ThreadID tid = interruptPriority; 1602 /* Evaluate interrupts in round-robin based upon service */ 1603 do { 1604 /* Has an interrupt been signalled? This may not be acted on 1605 * straighaway so this is different from took_interrupt */ 1606 bool thread_interrupted = false; 1607 1608 if (FullSystem && cpu.getInterruptController(tid)) { 1609 /* This is here because it seems that after drainResume the 1610 * interrupt controller isn't always set */ 1611 thread_interrupted = executeInfo[tid].drainState == NotDraining && 1612 isInterrupted(tid); 1613 interrupted = interrupted || thread_interrupted; 1614 } else { 1615 DPRINTF(MinorInterrupt, "No interrupt controller\n"); 1616 } 1617 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n", 1618 tid, thread_interrupted, isInbetweenInsts(tid)); 1619 /* Act on interrupts */ 1620 if (thread_interrupted && isInbetweenInsts(tid)) { 1621 if (takeInterrupt(tid, branch)) { 1622 interruptPriority = tid; 1623 return tid; 1624 } 1625 } else { 1626 tid = (tid + 1) % cpu.numThreads; 1627 } 1628 } while (tid != interruptPriority); 1629 1630 return InvalidThreadID; 1631} 1632 1633bool 1634Execute::hasInterrupt(ThreadID thread_id) 1635{ 1636 if (FullSystem && cpu.getInterruptController(thread_id)) { 1637 return executeInfo[thread_id].drainState == NotDraining && 1638 isInterrupted(thread_id); 1639 } 1640 1641 return false; 1642} 1643 1644void 1645Execute::minorTrace() const 1646{ 1647 std::ostringstream insts; 1648 std::ostringstream stalled; 1649 1650 executeInfo[0].instsBeingCommitted.reportData(insts); 1651 lsq.minorTrace(); 1652 inputBuffer[0].minorTrace(); 1653 scoreboard[0].minorTrace(); 1654 1655 /* Report functional unit stalling in one string */ 1656 unsigned int i = 0; 1657 while (i < numFuncUnits) 1658 { 1659 stalled << (funcUnits[i]->stalled ? '1' : 'E'); 1660 i++; 1661 if (i != numFuncUnits) 1662 stalled << ','; 1663 } 1664 1665 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d" 1666 " stalled=%s drainState=%d isInbetweenInsts=%d\n", 1667 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum, 1668 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0)); 1669 1670 std::for_each(funcUnits.begin(), funcUnits.end(), 1671 std::mem_fun(&FUPipeline::minorTrace)); 1672 1673 executeInfo[0].inFlightInsts->minorTrace(); 1674 executeInfo[0].inFUMemInsts->minorTrace(); 1675} 1676 1677inline ThreadID 1678Execute::getCommittingThread() 1679{ 1680 std::vector<ThreadID> priority_list; 1681 1682 switch (cpu.threadPolicy) { 1683 case Enums::SingleThreaded: 1684 return 0; 1685 case Enums::RoundRobin: 1686 priority_list = cpu.roundRobinPriority(commitPriority); 1687 break; 1688 case Enums::Random: 1689 priority_list = cpu.randomPriority(); 1690 break; 1691 default: 1692 panic("Invalid thread policy"); 1693 } 1694 1695 for (auto tid : priority_list) { 1696 ExecuteThreadInfo &ex_info = executeInfo[tid]; 1697 bool can_commit_insts = !ex_info.inFlightInsts->empty(); 1698 if (can_commit_insts) { 1699 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1700 MinorDynInstPtr inst = head_inflight_inst->inst; 1701 1702 can_commit_insts = can_commit_insts && 1703 (!inst->inLSQ || (lsq.findResponse(inst) != NULL)); 1704 1705 if (!inst->inLSQ) { 1706 bool can_transfer_mem_inst = false; 1707 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1708 const MinorDynInstPtr head_mem_ref_inst = 1709 ex_info.inFUMemInsts->front().inst; 1710 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1711 const MinorDynInstPtr &fu_inst = fu->front().inst; 1712 can_transfer_mem_inst = 1713 !fu_inst->isBubble() && 1714 fu_inst->id.threadId == tid && 1715 !fu_inst->inLSQ && 1716 fu_inst->canEarlyIssue && 1717 inst->id.execSeqNum > fu_inst->instToWaitFor; 1718 } 1719 1720 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex; 1721 if (can_commit_insts && !can_transfer_mem_inst && 1722 inst->fuIndex != noCostFUIndex) 1723 { 1724 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front(); 1725 can_execute_fu_inst = !fu_inst.inst->isBubble() && 1726 fu_inst.inst->id == inst->id; 1727 } 1728 1729 can_commit_insts = can_commit_insts && 1730 (can_transfer_mem_inst || can_execute_fu_inst); 1731 } 1732 } 1733 1734 1735 if (can_commit_insts) { 1736 commitPriority = tid; 1737 return tid; 1738 } 1739 } 1740 1741 return InvalidThreadID; 1742} 1743 1744inline ThreadID 1745Execute::getIssuingThread() 1746{ 1747 std::vector<ThreadID> priority_list; 1748 1749 switch (cpu.threadPolicy) { 1750 case Enums::SingleThreaded: 1751 return 0; 1752 case Enums::RoundRobin: 1753 priority_list = cpu.roundRobinPriority(issuePriority); 1754 break; 1755 case Enums::Random: 1756 priority_list = cpu.randomPriority(); 1757 break; 1758 default: 1759 panic("Invalid thread scheduling policy."); 1760 } 1761 1762 for (auto tid : priority_list) { 1763 if (getInput(tid)) { 1764 issuePriority = tid; 1765 return tid; 1766 } 1767 } 1768 1769 return InvalidThreadID; 1770} 1771 1772void 1773Execute::drainResume() 1774{ 1775 DPRINTF(Drain, "MinorExecute drainResume\n"); 1776 1777 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1778 setDrainState(tid, NotDraining); 1779 } 1780 1781 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1782} 1783 1784std::ostream &operator <<(std::ostream &os, Execute::DrainState state) 1785{ 1786 switch (state) 1787 { 1788 case Execute::NotDraining: 1789 os << "NotDraining"; 1790 break; 1791 case Execute::DrainCurrentInst: 1792 os << "DrainCurrentInst"; 1793 break; 1794 case Execute::DrainHaltFetch: 1795 os << "DrainHaltFetch"; 1796 break; 1797 case Execute::DrainAllInsts: 1798 os << "DrainAllInsts"; 1799 break; 1800 default: 1801 os << "Drain-" << static_cast<int>(state); 1802 break; 1803 } 1804 1805 return os; 1806} 1807 1808void 1809Execute::setDrainState(ThreadID thread_id, DrainState state) 1810{ 1811 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state); 1812 executeInfo[thread_id].drainState = state; 1813} 1814 1815unsigned int 1816Execute::drain() 1817{ 1818 DPRINTF(Drain, "MinorExecute drain\n"); 1819 1820 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1821 if (executeInfo[tid].drainState == NotDraining) { 1822 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1823 1824 /* Go to DrainCurrentInst if we're between microops 1825 * or waiting on an unbufferable memory operation. 1826 * Otherwise we can go straight to DrainHaltFetch 1827 */ 1828 if (isInbetweenInsts(tid)) 1829 setDrainState(tid, DrainHaltFetch); 1830 else 1831 setDrainState(tid, DrainCurrentInst); 1832 } 1833 } 1834 return (isDrained() ? 0 : 1); 1835} 1836 1837bool 1838Execute::isDrained() 1839{ 1840 if (!lsq.isDrained()) 1841 return false; 1842 1843 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1844 if (!inputBuffer[tid].empty() || 1845 !executeInfo[tid].inFlightInsts->empty()) { 1846 1847 return false; 1848 } 1849 } 1850 1851 return true; 1852} 1853 1854Execute::~Execute() 1855{ 1856 for (unsigned int i = 0; i < numFuncUnits; i++) 1857 delete funcUnits[i]; 1858 1859 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) 1860 delete executeInfo[tid].inFlightInsts; 1861} 1862 1863bool 1864Execute::instIsRightStream(MinorDynInstPtr inst) 1865{ 1866 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum; 1867} 1868 1869bool 1870Execute::instIsHeadInst(MinorDynInstPtr inst) 1871{ 1872 bool ret = false; 1873 1874 if (!executeInfo[inst->id.threadId].inFlightInsts->empty()) 1875 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id; 1876 1877 return ret; 1878} 1879 1880MinorCPU::MinorCPUPort & 1881Execute::getDcachePort() 1882{ 1883 return lsq.getDcachePort(); 1884} 1885 1886} 1887