exec_context.hh revision 14105
110259SAndrew.Bardsley@arm.com/* 213953Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2014, 2016-2018 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4310259SAndrew.Bardsley@arm.com * Nathan Binkert 4410259SAndrew.Bardsley@arm.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4910259SAndrew.Bardsley@arm.com * 5010259SAndrew.Bardsley@arm.com * ExecContext bears the exec_context interface for Minor. 5110259SAndrew.Bardsley@arm.com */ 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 6210259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comnamespace Minor 6510259SAndrew.Bardsley@arm.com{ 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6810259SAndrew.Bardsley@arm.comclass Execute; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7110259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7210259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7310259SAndrew.Bardsley@arm.com */ 7410319SAndreas.Sandberg@ARM.comclass ExecContext : public ::ExecContext 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 8010259SAndrew.Bardsley@arm.com SimpleThread &thread; 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8310259SAndrew.Bardsley@arm.com Execute &execute; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8610259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com ExecContext ( 8910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 9010259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9210259SAndrew.Bardsley@arm.com cpu(cpu_), 9310259SAndrew.Bardsley@arm.com thread(thread_), 9410259SAndrew.Bardsley@arm.com execute(execute_), 9510259SAndrew.Bardsley@arm.com inst(inst_) 9610259SAndrew.Bardsley@arm.com { 9710259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9810259SAndrew.Bardsley@arm.com pcState(inst->pc); 9913954Sgiacomo.gabrielli@arm.com setPredicate(inst->readPredicate()); 10013954Sgiacomo.gabrielli@arm.com setMemAccPredicate(inst->readMemAccPredicate()); 10110259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10210259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10313611Sgabeblack@google.com thread.setFloatReg(TheISA::ZeroReg, 0); 10410259SAndrew.Bardsley@arm.com#endif 10510259SAndrew.Bardsley@arm.com } 10610259SAndrew.Bardsley@arm.com 10713954Sgiacomo.gabrielli@arm.com ~ExecContext() 10813954Sgiacomo.gabrielli@arm.com { 10913954Sgiacomo.gabrielli@arm.com inst->setPredicate(readPredicate()); 11013954Sgiacomo.gabrielli@arm.com inst->setMemAccPredicate(readMemAccPredicate()); 11113954Sgiacomo.gabrielli@arm.com } 11213954Sgiacomo.gabrielli@arm.com 11310259SAndrew.Bardsley@arm.com Fault 11411612Sandreas.sandberg@arm.com initiateMemRead(Addr addr, unsigned int size, 11513954Sgiacomo.gabrielli@arm.com Request::Flags flags, 11613954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 11713954Sgiacomo.gabrielli@arm.com override 11810259SAndrew.Bardsley@arm.com { 11914105Sgabor.dozsa@arm.com return execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 12013954Sgiacomo.gabrielli@arm.com size, addr, flags, nullptr, nullptr, byteEnable); 12110259SAndrew.Bardsley@arm.com } 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com Fault 12410259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 12513954Sgiacomo.gabrielli@arm.com Request::Flags flags, uint64_t *res, 12613954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 12713954Sgiacomo.gabrielli@arm.com override 12810259SAndrew.Bardsley@arm.com { 12913954Sgiacomo.gabrielli@arm.com assert(byteEnable.empty() || byteEnable.size() == size); 13014105Sgabor.dozsa@arm.com return execute.getLSQ().pushRequest(inst, false /* store */, data, 13113954Sgiacomo.gabrielli@arm.com size, addr, flags, res, nullptr, byteEnable); 13213652Sqtt2@cornell.edu } 13313652Sqtt2@cornell.edu 13413652Sqtt2@cornell.edu Fault 13513652Sqtt2@cornell.edu initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, 13613652Sqtt2@cornell.edu AtomicOpFunctor *amo_op) override 13713652Sqtt2@cornell.edu { 13813652Sqtt2@cornell.edu // AMO requests are pushed through the store path 13914105Sgabor.dozsa@arm.com return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr, 14013652Sqtt2@cornell.edu size, addr, flags, nullptr, amo_op); 14110259SAndrew.Bardsley@arm.com } 14210259SAndrew.Bardsley@arm.com 14313557Sgabeblack@google.com RegVal 14411611SReiley.Jeyapaul@arm.com readIntRegOperand(const StaticInst *si, int idx) override 14510259SAndrew.Bardsley@arm.com { 14612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 14712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 14812106SRekai.GonzalezAlberquilla@arm.com return thread.readIntReg(reg.index()); 14910259SAndrew.Bardsley@arm.com } 15010259SAndrew.Bardsley@arm.com 15113557Sgabeblack@google.com RegVal 15211611SReiley.Jeyapaul@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 15310259SAndrew.Bardsley@arm.com { 15412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 15512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 15613611Sgabeblack@google.com return thread.readFloatReg(reg.index()); 15710259SAndrew.Bardsley@arm.com } 15810259SAndrew.Bardsley@arm.com 15913557Sgabeblack@google.com const TheISA::VecRegContainer & 16012109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 16112109SRekai.GonzalezAlberquilla@arm.com { 16212109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 16312109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 16412109SRekai.GonzalezAlberquilla@arm.com return thread.readVecReg(reg); 16512109SRekai.GonzalezAlberquilla@arm.com } 16612109SRekai.GonzalezAlberquilla@arm.com 16713557Sgabeblack@google.com TheISA::VecRegContainer & 16812109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 16912109SRekai.GonzalezAlberquilla@arm.com { 17012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 17112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 17212109SRekai.GonzalezAlberquilla@arm.com return thread.getWritableVecReg(reg); 17312109SRekai.GonzalezAlberquilla@arm.com } 17412109SRekai.GonzalezAlberquilla@arm.com 17512109SRekai.GonzalezAlberquilla@arm.com TheISA::VecElem 17612109SRekai.GonzalezAlberquilla@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 17712109SRekai.GonzalezAlberquilla@arm.com { 17812109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 17913598Sgiacomo.travaglini@arm.com assert(reg.isVecElem()); 18012109SRekai.GonzalezAlberquilla@arm.com return thread.readVecElem(reg); 18112109SRekai.GonzalezAlberquilla@arm.com } 18212109SRekai.GonzalezAlberquilla@arm.com 18313610Sgiacomo.gabrielli@arm.com const TheISA::VecPredRegContainer& 18413610Sgiacomo.gabrielli@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const override 18513610Sgiacomo.gabrielli@arm.com { 18613610Sgiacomo.gabrielli@arm.com const RegId& reg = si->srcRegIdx(idx); 18713610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 18813610Sgiacomo.gabrielli@arm.com return thread.readVecPredReg(reg); 18913610Sgiacomo.gabrielli@arm.com } 19013610Sgiacomo.gabrielli@arm.com 19113610Sgiacomo.gabrielli@arm.com TheISA::VecPredRegContainer& 19213610Sgiacomo.gabrielli@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) override 19313610Sgiacomo.gabrielli@arm.com { 19413610Sgiacomo.gabrielli@arm.com const RegId& reg = si->destRegIdx(idx); 19513610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 19613610Sgiacomo.gabrielli@arm.com return thread.getWritableVecPredReg(reg); 19713610Sgiacomo.gabrielli@arm.com } 19813610Sgiacomo.gabrielli@arm.com 19910259SAndrew.Bardsley@arm.com void 20013557Sgabeblack@google.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 20110259SAndrew.Bardsley@arm.com { 20212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 20312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 20412106SRekai.GonzalezAlberquilla@arm.com thread.setIntReg(reg.index(), val); 20510259SAndrew.Bardsley@arm.com } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com void 20813557Sgabeblack@google.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 20910259SAndrew.Bardsley@arm.com { 21012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 21112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21213611Sgabeblack@google.com thread.setFloatReg(reg.index(), val); 21310259SAndrew.Bardsley@arm.com } 21410259SAndrew.Bardsley@arm.com 21512109SRekai.GonzalezAlberquilla@arm.com void 21612109SRekai.GonzalezAlberquilla@arm.com setVecRegOperand(const StaticInst *si, int idx, 21712109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecRegContainer& val) override 21812109SRekai.GonzalezAlberquilla@arm.com { 21912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 22012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22112109SRekai.GonzalezAlberquilla@arm.com thread.setVecReg(reg, val); 22212109SRekai.GonzalezAlberquilla@arm.com } 22312109SRekai.GonzalezAlberquilla@arm.com 22413610Sgiacomo.gabrielli@arm.com void 22513610Sgiacomo.gabrielli@arm.com setVecPredRegOperand(const StaticInst *si, int idx, 22613628SAndrea.Mondelli@ucf.edu const TheISA::VecPredRegContainer& val) override 22713610Sgiacomo.gabrielli@arm.com { 22813610Sgiacomo.gabrielli@arm.com const RegId& reg = si->destRegIdx(idx); 22913610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 23013610Sgiacomo.gabrielli@arm.com thread.setVecPredReg(reg, val); 23113610Sgiacomo.gabrielli@arm.com } 23213610Sgiacomo.gabrielli@arm.com 23312109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 23412109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 23512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 23612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 23712109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 23812109SRekai.GonzalezAlberquilla@arm.com override 23912109SRekai.GonzalezAlberquilla@arm.com { 24012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 24112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24212109SRekai.GonzalezAlberquilla@arm.com return thread.readVec8BitLaneReg(reg); 24312109SRekai.GonzalezAlberquilla@arm.com } 24412109SRekai.GonzalezAlberquilla@arm.com 24512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 24612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 24712109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 24812109SRekai.GonzalezAlberquilla@arm.com override 24912109SRekai.GonzalezAlberquilla@arm.com { 25012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 25112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25212109SRekai.GonzalezAlberquilla@arm.com return thread.readVec16BitLaneReg(reg); 25312109SRekai.GonzalezAlberquilla@arm.com } 25412109SRekai.GonzalezAlberquilla@arm.com 25512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 25612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 25712109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 25812109SRekai.GonzalezAlberquilla@arm.com override 25912109SRekai.GonzalezAlberquilla@arm.com { 26012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 26112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26212109SRekai.GonzalezAlberquilla@arm.com return thread.readVec32BitLaneReg(reg); 26312109SRekai.GonzalezAlberquilla@arm.com } 26412109SRekai.GonzalezAlberquilla@arm.com 26512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 26612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 26712109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 26812109SRekai.GonzalezAlberquilla@arm.com override 26912109SRekai.GonzalezAlberquilla@arm.com { 27012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 27112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27212109SRekai.GonzalezAlberquilla@arm.com return thread.readVec64BitLaneReg(reg); 27312109SRekai.GonzalezAlberquilla@arm.com } 27412109SRekai.GonzalezAlberquilla@arm.com 27512109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 27612109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 27712109SRekai.GonzalezAlberquilla@arm.com void 27813557Sgabeblack@google.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 27912109SRekai.GonzalezAlberquilla@arm.com { 28012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 28112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 28212109SRekai.GonzalezAlberquilla@arm.com return thread.setVecLane(reg, val); 28312109SRekai.GonzalezAlberquilla@arm.com } 28412109SRekai.GonzalezAlberquilla@arm.com virtual void 28512109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 28612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 28712109SRekai.GonzalezAlberquilla@arm.com { 28812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 28912109SRekai.GonzalezAlberquilla@arm.com } 29012109SRekai.GonzalezAlberquilla@arm.com virtual void 29112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 29312109SRekai.GonzalezAlberquilla@arm.com { 29412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29512109SRekai.GonzalezAlberquilla@arm.com } 29612109SRekai.GonzalezAlberquilla@arm.com virtual void 29712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 29912109SRekai.GonzalezAlberquilla@arm.com { 30012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30112109SRekai.GonzalezAlberquilla@arm.com } 30212109SRekai.GonzalezAlberquilla@arm.com virtual void 30312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 30512109SRekai.GonzalezAlberquilla@arm.com { 30612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30712109SRekai.GonzalezAlberquilla@arm.com } 30812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 30912109SRekai.GonzalezAlberquilla@arm.com 31012109SRekai.GonzalezAlberquilla@arm.com void 31112109SRekai.GonzalezAlberquilla@arm.com setVecElemOperand(const StaticInst *si, int idx, 31212109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecElem val) override 31312109SRekai.GonzalezAlberquilla@arm.com { 31412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 31513598Sgiacomo.travaglini@arm.com assert(reg.isVecElem()); 31612109SRekai.GonzalezAlberquilla@arm.com thread.setVecElem(reg, val); 31712109SRekai.GonzalezAlberquilla@arm.com } 31812109SRekai.GonzalezAlberquilla@arm.com 31910259SAndrew.Bardsley@arm.com bool 32013429Srekai.gonzalezalberquilla@arm.com readPredicate() const override 32110259SAndrew.Bardsley@arm.com { 32210259SAndrew.Bardsley@arm.com return thread.readPredicate(); 32310259SAndrew.Bardsley@arm.com } 32410259SAndrew.Bardsley@arm.com 32510259SAndrew.Bardsley@arm.com void 32611611SReiley.Jeyapaul@arm.com setPredicate(bool val) override 32710259SAndrew.Bardsley@arm.com { 32810259SAndrew.Bardsley@arm.com thread.setPredicate(val); 32910259SAndrew.Bardsley@arm.com } 33010259SAndrew.Bardsley@arm.com 33113953Sgiacomo.gabrielli@arm.com bool 33213953Sgiacomo.gabrielli@arm.com readMemAccPredicate() const override 33313953Sgiacomo.gabrielli@arm.com { 33413953Sgiacomo.gabrielli@arm.com return thread.readMemAccPredicate(); 33513953Sgiacomo.gabrielli@arm.com } 33613953Sgiacomo.gabrielli@arm.com 33713953Sgiacomo.gabrielli@arm.com void 33813953Sgiacomo.gabrielli@arm.com setMemAccPredicate(bool val) override 33913953Sgiacomo.gabrielli@arm.com { 34013953Sgiacomo.gabrielli@arm.com thread.setMemAccPredicate(val); 34113953Sgiacomo.gabrielli@arm.com } 34213953Sgiacomo.gabrielli@arm.com 34310259SAndrew.Bardsley@arm.com TheISA::PCState 34411611SReiley.Jeyapaul@arm.com pcState() const override 34510259SAndrew.Bardsley@arm.com { 34610259SAndrew.Bardsley@arm.com return thread.pcState(); 34710259SAndrew.Bardsley@arm.com } 34810259SAndrew.Bardsley@arm.com 34910259SAndrew.Bardsley@arm.com void 35011611SReiley.Jeyapaul@arm.com pcState(const TheISA::PCState &val) override 35110259SAndrew.Bardsley@arm.com { 35210259SAndrew.Bardsley@arm.com thread.pcState(val); 35310259SAndrew.Bardsley@arm.com } 35410259SAndrew.Bardsley@arm.com 35513557Sgabeblack@google.com RegVal 35610698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg) const 35710259SAndrew.Bardsley@arm.com { 35810259SAndrew.Bardsley@arm.com return thread.readMiscRegNoEffect(misc_reg); 35910259SAndrew.Bardsley@arm.com } 36010259SAndrew.Bardsley@arm.com 36113557Sgabeblack@google.com RegVal 36211611SReiley.Jeyapaul@arm.com readMiscReg(int misc_reg) override 36310259SAndrew.Bardsley@arm.com { 36410259SAndrew.Bardsley@arm.com return thread.readMiscReg(misc_reg); 36510259SAndrew.Bardsley@arm.com } 36610259SAndrew.Bardsley@arm.com 36710259SAndrew.Bardsley@arm.com void 36813582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val) override 36910259SAndrew.Bardsley@arm.com { 37010259SAndrew.Bardsley@arm.com thread.setMiscReg(misc_reg, val); 37110259SAndrew.Bardsley@arm.com } 37210259SAndrew.Bardsley@arm.com 37313557Sgabeblack@google.com RegVal 37411611SReiley.Jeyapaul@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 37510259SAndrew.Bardsley@arm.com { 37612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 37712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 37812106SRekai.GonzalezAlberquilla@arm.com return thread.readMiscReg(reg.index()); 37910259SAndrew.Bardsley@arm.com } 38010259SAndrew.Bardsley@arm.com 38110259SAndrew.Bardsley@arm.com void 38213582Sgabeblack@google.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 38310259SAndrew.Bardsley@arm.com { 38412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 38612106SRekai.GonzalezAlberquilla@arm.com return thread.setMiscReg(reg.index(), val); 38710259SAndrew.Bardsley@arm.com } 38810259SAndrew.Bardsley@arm.com 38910259SAndrew.Bardsley@arm.com void 39011877Sbrandon.potter@amd.com syscall(int64_t callnum, Fault *fault) override 39113557Sgabeblack@google.com { 39210259SAndrew.Bardsley@arm.com if (FullSystem) 39310259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode.\n"); 39410259SAndrew.Bardsley@arm.com 39511877Sbrandon.potter@amd.com thread.syscall(callnum, fault); 39610259SAndrew.Bardsley@arm.com } 39710259SAndrew.Bardsley@arm.com 39811611SReiley.Jeyapaul@arm.com ThreadContext *tcBase() override { return thread.getTC(); } 39910259SAndrew.Bardsley@arm.com 40010259SAndrew.Bardsley@arm.com /* @todo, should make stCondFailures persistent somewhere */ 40111611SReiley.Jeyapaul@arm.com unsigned int readStCondFailures() const override { return 0; } 40211611SReiley.Jeyapaul@arm.com void setStCondFailures(unsigned int st_cond_failures) override {} 40310259SAndrew.Bardsley@arm.com 40411005Sandreas.sandberg@arm.com ContextID contextId() { return thread.contextId(); } 40510259SAndrew.Bardsley@arm.com /* ISA-specific (or at least currently ISA singleton) functions */ 40610259SAndrew.Bardsley@arm.com 40710259SAndrew.Bardsley@arm.com /* X86: TLB twiddling */ 40810259SAndrew.Bardsley@arm.com void 40911611SReiley.Jeyapaul@arm.com demapPage(Addr vaddr, uint64_t asn) override 41010259SAndrew.Bardsley@arm.com { 41110259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 41210259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 41310259SAndrew.Bardsley@arm.com } 41410259SAndrew.Bardsley@arm.com 41513622Sgabeblack@google.com RegVal 41611611SReiley.Jeyapaul@arm.com readCCRegOperand(const StaticInst *si, int idx) override 41710935Snilay@cs.wisc.edu { 41812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 41912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 42012106SRekai.GonzalezAlberquilla@arm.com return thread.readCCReg(reg.index()); 42110935Snilay@cs.wisc.edu } 42210935Snilay@cs.wisc.edu 42310935Snilay@cs.wisc.edu void 42413622Sgabeblack@google.com setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 42510935Snilay@cs.wisc.edu { 42612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 42712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 42812106SRekai.GonzalezAlberquilla@arm.com thread.setCCReg(reg.index(), val); 42910935Snilay@cs.wisc.edu } 43010935Snilay@cs.wisc.edu 43110259SAndrew.Bardsley@arm.com void 43210259SAndrew.Bardsley@arm.com demapInstPage(Addr vaddr, uint64_t asn) 43310259SAndrew.Bardsley@arm.com { 43410259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 43510259SAndrew.Bardsley@arm.com } 43610259SAndrew.Bardsley@arm.com 43710259SAndrew.Bardsley@arm.com void 43810259SAndrew.Bardsley@arm.com demapDataPage(Addr vaddr, uint64_t asn) 43910259SAndrew.Bardsley@arm.com { 44010259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 44110259SAndrew.Bardsley@arm.com } 44210259SAndrew.Bardsley@arm.com 44310259SAndrew.Bardsley@arm.com BaseCPU *getCpuPtr() { return &cpu; } 44410259SAndrew.Bardsley@arm.com 44510529Smorr@cs.wisc.edu public: 44610529Smorr@cs.wisc.edu // monitor/mwait funtions 44711611SReiley.Jeyapaul@arm.com void armMonitor(Addr address) override 44811567Smitch.hayenga@arm.com { getCpuPtr()->armMonitor(inst->id.threadId, address); } 44911567Smitch.hayenga@arm.com 45011611SReiley.Jeyapaul@arm.com bool mwait(PacketPtr pkt) override 45111567Smitch.hayenga@arm.com { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 45211567Smitch.hayenga@arm.com 45311611SReiley.Jeyapaul@arm.com void mwaitAtomic(ThreadContext *tc) override 45411567Smitch.hayenga@arm.com { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 45511567Smitch.hayenga@arm.com 45611611SReiley.Jeyapaul@arm.com AddressMonitor *getAddrMonitor() override 45711567Smitch.hayenga@arm.com { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 45810259SAndrew.Bardsley@arm.com}; 45910259SAndrew.Bardsley@arm.com 46010259SAndrew.Bardsley@arm.com} 46110259SAndrew.Bardsley@arm.com 46210259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 463