exec_context.hh revision 13582
110259SAndrew.Bardsley@arm.com/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2014, 2016 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4310259SAndrew.Bardsley@arm.com * Nathan Binkert 4410259SAndrew.Bardsley@arm.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4910259SAndrew.Bardsley@arm.com * 5010259SAndrew.Bardsley@arm.com * ExecContext bears the exec_context interface for Minor. 5110259SAndrew.Bardsley@arm.com */ 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 6210259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comnamespace Minor 6510259SAndrew.Bardsley@arm.com{ 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6810259SAndrew.Bardsley@arm.comclass Execute; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7110259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7210259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7310259SAndrew.Bardsley@arm.com */ 7410319SAndreas.Sandberg@ARM.comclass ExecContext : public ::ExecContext 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 8010259SAndrew.Bardsley@arm.com SimpleThread &thread; 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8310259SAndrew.Bardsley@arm.com Execute &execute; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8610259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com ExecContext ( 8910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 9010259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9210259SAndrew.Bardsley@arm.com cpu(cpu_), 9310259SAndrew.Bardsley@arm.com thread(thread_), 9410259SAndrew.Bardsley@arm.com execute(execute_), 9510259SAndrew.Bardsley@arm.com inst(inst_) 9610259SAndrew.Bardsley@arm.com { 9710259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9810259SAndrew.Bardsley@arm.com pcState(inst->pc); 9910259SAndrew.Bardsley@arm.com setPredicate(true); 10010259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10110259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10213500Sgabeblack@google.com thread.setFloatRegBits(TheISA::ZeroReg, 0); 10310259SAndrew.Bardsley@arm.com#endif 10410259SAndrew.Bardsley@arm.com } 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com Fault 10711612Sandreas.sandberg@arm.com initiateMemRead(Addr addr, unsigned int size, 10811612Sandreas.sandberg@arm.com Request::Flags flags) override 10910259SAndrew.Bardsley@arm.com { 11011303Ssteve.reinhardt@amd.com execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 11110259SAndrew.Bardsley@arm.com size, addr, flags, NULL); 11210259SAndrew.Bardsley@arm.com return NoFault; 11310259SAndrew.Bardsley@arm.com } 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com Fault 11610259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 11711611SReiley.Jeyapaul@arm.com Request::Flags flags, uint64_t *res) override 11810259SAndrew.Bardsley@arm.com { 11910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* store */, data, 12010259SAndrew.Bardsley@arm.com size, addr, flags, res); 12110259SAndrew.Bardsley@arm.com return NoFault; 12210259SAndrew.Bardsley@arm.com } 12310259SAndrew.Bardsley@arm.com 12413557Sgabeblack@google.com RegVal 12511611SReiley.Jeyapaul@arm.com readIntRegOperand(const StaticInst *si, int idx) override 12610259SAndrew.Bardsley@arm.com { 12712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 12812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 12912106SRekai.GonzalezAlberquilla@arm.com return thread.readIntReg(reg.index()); 13010259SAndrew.Bardsley@arm.com } 13110259SAndrew.Bardsley@arm.com 13213557Sgabeblack@google.com RegVal 13311611SReiley.Jeyapaul@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 13410259SAndrew.Bardsley@arm.com { 13512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 13612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 13712106SRekai.GonzalezAlberquilla@arm.com return thread.readFloatRegBits(reg.index()); 13810259SAndrew.Bardsley@arm.com } 13910259SAndrew.Bardsley@arm.com 14013557Sgabeblack@google.com const TheISA::VecRegContainer & 14112109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 14212109SRekai.GonzalezAlberquilla@arm.com { 14312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 14412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 14512109SRekai.GonzalezAlberquilla@arm.com return thread.readVecReg(reg); 14612109SRekai.GonzalezAlberquilla@arm.com } 14712109SRekai.GonzalezAlberquilla@arm.com 14813557Sgabeblack@google.com TheISA::VecRegContainer & 14912109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 15012109SRekai.GonzalezAlberquilla@arm.com { 15112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 15212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 15312109SRekai.GonzalezAlberquilla@arm.com return thread.getWritableVecReg(reg); 15412109SRekai.GonzalezAlberquilla@arm.com } 15512109SRekai.GonzalezAlberquilla@arm.com 15612109SRekai.GonzalezAlberquilla@arm.com TheISA::VecElem 15712109SRekai.GonzalezAlberquilla@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 15812109SRekai.GonzalezAlberquilla@arm.com { 15912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 16012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 16112109SRekai.GonzalezAlberquilla@arm.com return thread.readVecElem(reg); 16212109SRekai.GonzalezAlberquilla@arm.com } 16312109SRekai.GonzalezAlberquilla@arm.com 16410259SAndrew.Bardsley@arm.com void 16513557Sgabeblack@google.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 16610259SAndrew.Bardsley@arm.com { 16712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 16812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 16912106SRekai.GonzalezAlberquilla@arm.com thread.setIntReg(reg.index(), val); 17010259SAndrew.Bardsley@arm.com } 17110259SAndrew.Bardsley@arm.com 17210259SAndrew.Bardsley@arm.com void 17313557Sgabeblack@google.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 17410259SAndrew.Bardsley@arm.com { 17512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 17612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 17712106SRekai.GonzalezAlberquilla@arm.com thread.setFloatRegBits(reg.index(), val); 17810259SAndrew.Bardsley@arm.com } 17910259SAndrew.Bardsley@arm.com 18012109SRekai.GonzalezAlberquilla@arm.com void 18112109SRekai.GonzalezAlberquilla@arm.com setVecRegOperand(const StaticInst *si, int idx, 18212109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecRegContainer& val) override 18312109SRekai.GonzalezAlberquilla@arm.com { 18412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 18512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 18612109SRekai.GonzalezAlberquilla@arm.com thread.setVecReg(reg, val); 18712109SRekai.GonzalezAlberquilla@arm.com } 18812109SRekai.GonzalezAlberquilla@arm.com 18912109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 19012109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 19112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 19212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 19312109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 19412109SRekai.GonzalezAlberquilla@arm.com override 19512109SRekai.GonzalezAlberquilla@arm.com { 19612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 19812109SRekai.GonzalezAlberquilla@arm.com return thread.readVec8BitLaneReg(reg); 19912109SRekai.GonzalezAlberquilla@arm.com } 20012109SRekai.GonzalezAlberquilla@arm.com 20112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 20212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 20312109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 20412109SRekai.GonzalezAlberquilla@arm.com override 20512109SRekai.GonzalezAlberquilla@arm.com { 20612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 20812109SRekai.GonzalezAlberquilla@arm.com return thread.readVec16BitLaneReg(reg); 20912109SRekai.GonzalezAlberquilla@arm.com } 21012109SRekai.GonzalezAlberquilla@arm.com 21112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 21212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 21312109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 21412109SRekai.GonzalezAlberquilla@arm.com override 21512109SRekai.GonzalezAlberquilla@arm.com { 21612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 21812109SRekai.GonzalezAlberquilla@arm.com return thread.readVec32BitLaneReg(reg); 21912109SRekai.GonzalezAlberquilla@arm.com } 22012109SRekai.GonzalezAlberquilla@arm.com 22112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 22212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 22312109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 22412109SRekai.GonzalezAlberquilla@arm.com override 22512109SRekai.GonzalezAlberquilla@arm.com { 22612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22812109SRekai.GonzalezAlberquilla@arm.com return thread.readVec64BitLaneReg(reg); 22912109SRekai.GonzalezAlberquilla@arm.com } 23012109SRekai.GonzalezAlberquilla@arm.com 23112109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 23212109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 23312109SRekai.GonzalezAlberquilla@arm.com void 23413557Sgabeblack@google.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 23512109SRekai.GonzalezAlberquilla@arm.com { 23612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23812109SRekai.GonzalezAlberquilla@arm.com return thread.setVecLane(reg, val); 23912109SRekai.GonzalezAlberquilla@arm.com } 24012109SRekai.GonzalezAlberquilla@arm.com virtual void 24112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 24212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 24312109SRekai.GonzalezAlberquilla@arm.com { 24412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 24512109SRekai.GonzalezAlberquilla@arm.com } 24612109SRekai.GonzalezAlberquilla@arm.com virtual void 24712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 24812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 24912109SRekai.GonzalezAlberquilla@arm.com { 25012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 25112109SRekai.GonzalezAlberquilla@arm.com } 25212109SRekai.GonzalezAlberquilla@arm.com virtual void 25312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 25412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 25512109SRekai.GonzalezAlberquilla@arm.com { 25612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 25712109SRekai.GonzalezAlberquilla@arm.com } 25812109SRekai.GonzalezAlberquilla@arm.com virtual void 25912109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 26012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 26112109SRekai.GonzalezAlberquilla@arm.com { 26212109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 26312109SRekai.GonzalezAlberquilla@arm.com } 26412109SRekai.GonzalezAlberquilla@arm.com /** @} */ 26512109SRekai.GonzalezAlberquilla@arm.com 26612109SRekai.GonzalezAlberquilla@arm.com void 26712109SRekai.GonzalezAlberquilla@arm.com setVecElemOperand(const StaticInst *si, int idx, 26812109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecElem val) override 26912109SRekai.GonzalezAlberquilla@arm.com { 27012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27212109SRekai.GonzalezAlberquilla@arm.com thread.setVecElem(reg, val); 27312109SRekai.GonzalezAlberquilla@arm.com } 27412109SRekai.GonzalezAlberquilla@arm.com 27510259SAndrew.Bardsley@arm.com bool 27613429Srekai.gonzalezalberquilla@arm.com readPredicate() const override 27710259SAndrew.Bardsley@arm.com { 27810259SAndrew.Bardsley@arm.com return thread.readPredicate(); 27910259SAndrew.Bardsley@arm.com } 28010259SAndrew.Bardsley@arm.com 28110259SAndrew.Bardsley@arm.com void 28211611SReiley.Jeyapaul@arm.com setPredicate(bool val) override 28310259SAndrew.Bardsley@arm.com { 28410259SAndrew.Bardsley@arm.com thread.setPredicate(val); 28510259SAndrew.Bardsley@arm.com } 28610259SAndrew.Bardsley@arm.com 28710259SAndrew.Bardsley@arm.com TheISA::PCState 28811611SReiley.Jeyapaul@arm.com pcState() const override 28910259SAndrew.Bardsley@arm.com { 29010259SAndrew.Bardsley@arm.com return thread.pcState(); 29110259SAndrew.Bardsley@arm.com } 29210259SAndrew.Bardsley@arm.com 29310259SAndrew.Bardsley@arm.com void 29411611SReiley.Jeyapaul@arm.com pcState(const TheISA::PCState &val) override 29510259SAndrew.Bardsley@arm.com { 29610259SAndrew.Bardsley@arm.com thread.pcState(val); 29710259SAndrew.Bardsley@arm.com } 29810259SAndrew.Bardsley@arm.com 29913557Sgabeblack@google.com RegVal 30010698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg) const 30110259SAndrew.Bardsley@arm.com { 30210259SAndrew.Bardsley@arm.com return thread.readMiscRegNoEffect(misc_reg); 30310259SAndrew.Bardsley@arm.com } 30410259SAndrew.Bardsley@arm.com 30513557Sgabeblack@google.com RegVal 30611611SReiley.Jeyapaul@arm.com readMiscReg(int misc_reg) override 30710259SAndrew.Bardsley@arm.com { 30810259SAndrew.Bardsley@arm.com return thread.readMiscReg(misc_reg); 30910259SAndrew.Bardsley@arm.com } 31010259SAndrew.Bardsley@arm.com 31110259SAndrew.Bardsley@arm.com void 31213582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val) override 31310259SAndrew.Bardsley@arm.com { 31410259SAndrew.Bardsley@arm.com thread.setMiscReg(misc_reg, val); 31510259SAndrew.Bardsley@arm.com } 31610259SAndrew.Bardsley@arm.com 31713557Sgabeblack@google.com RegVal 31811611SReiley.Jeyapaul@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 31910259SAndrew.Bardsley@arm.com { 32012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 32212106SRekai.GonzalezAlberquilla@arm.com return thread.readMiscReg(reg.index()); 32310259SAndrew.Bardsley@arm.com } 32410259SAndrew.Bardsley@arm.com 32510259SAndrew.Bardsley@arm.com void 32613582Sgabeblack@google.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 32710259SAndrew.Bardsley@arm.com { 32812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 32912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 33012106SRekai.GonzalezAlberquilla@arm.com return thread.setMiscReg(reg.index(), val); 33110259SAndrew.Bardsley@arm.com } 33210259SAndrew.Bardsley@arm.com 33310259SAndrew.Bardsley@arm.com Fault 33411611SReiley.Jeyapaul@arm.com hwrei() override 33510259SAndrew.Bardsley@arm.com { 33610259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 33710259SAndrew.Bardsley@arm.com return thread.hwrei(); 33810259SAndrew.Bardsley@arm.com#else 33910259SAndrew.Bardsley@arm.com return NoFault; 34010259SAndrew.Bardsley@arm.com#endif 34110259SAndrew.Bardsley@arm.com } 34210259SAndrew.Bardsley@arm.com 34310259SAndrew.Bardsley@arm.com bool 34411611SReiley.Jeyapaul@arm.com simPalCheck(int palFunc) override 34510259SAndrew.Bardsley@arm.com { 34610259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 34710259SAndrew.Bardsley@arm.com return thread.simPalCheck(palFunc); 34810259SAndrew.Bardsley@arm.com#else 34910259SAndrew.Bardsley@arm.com return false; 35010259SAndrew.Bardsley@arm.com#endif 35110259SAndrew.Bardsley@arm.com } 35210259SAndrew.Bardsley@arm.com 35310259SAndrew.Bardsley@arm.com void 35411877Sbrandon.potter@amd.com syscall(int64_t callnum, Fault *fault) override 35513557Sgabeblack@google.com { 35610259SAndrew.Bardsley@arm.com if (FullSystem) 35710259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode.\n"); 35810259SAndrew.Bardsley@arm.com 35911877Sbrandon.potter@amd.com thread.syscall(callnum, fault); 36010259SAndrew.Bardsley@arm.com } 36110259SAndrew.Bardsley@arm.com 36211611SReiley.Jeyapaul@arm.com ThreadContext *tcBase() override { return thread.getTC(); } 36310259SAndrew.Bardsley@arm.com 36410259SAndrew.Bardsley@arm.com /* @todo, should make stCondFailures persistent somewhere */ 36511611SReiley.Jeyapaul@arm.com unsigned int readStCondFailures() const override { return 0; } 36611611SReiley.Jeyapaul@arm.com void setStCondFailures(unsigned int st_cond_failures) override {} 36710259SAndrew.Bardsley@arm.com 36811005Sandreas.sandberg@arm.com ContextID contextId() { return thread.contextId(); } 36910259SAndrew.Bardsley@arm.com /* ISA-specific (or at least currently ISA singleton) functions */ 37010259SAndrew.Bardsley@arm.com 37110259SAndrew.Bardsley@arm.com /* X86: TLB twiddling */ 37210259SAndrew.Bardsley@arm.com void 37311611SReiley.Jeyapaul@arm.com demapPage(Addr vaddr, uint64_t asn) override 37410259SAndrew.Bardsley@arm.com { 37510259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 37610259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 37710259SAndrew.Bardsley@arm.com } 37810259SAndrew.Bardsley@arm.com 37910935Snilay@cs.wisc.edu TheISA::CCReg 38011611SReiley.Jeyapaul@arm.com readCCRegOperand(const StaticInst *si, int idx) override 38110935Snilay@cs.wisc.edu { 38212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 38312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 38412106SRekai.GonzalezAlberquilla@arm.com return thread.readCCReg(reg.index()); 38510935Snilay@cs.wisc.edu } 38610935Snilay@cs.wisc.edu 38710935Snilay@cs.wisc.edu void 38811611SReiley.Jeyapaul@arm.com setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override 38910935Snilay@cs.wisc.edu { 39012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 39112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 39212106SRekai.GonzalezAlberquilla@arm.com thread.setCCReg(reg.index(), val); 39310935Snilay@cs.wisc.edu } 39410935Snilay@cs.wisc.edu 39510259SAndrew.Bardsley@arm.com void 39610259SAndrew.Bardsley@arm.com demapInstPage(Addr vaddr, uint64_t asn) 39710259SAndrew.Bardsley@arm.com { 39810259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 39910259SAndrew.Bardsley@arm.com } 40010259SAndrew.Bardsley@arm.com 40110259SAndrew.Bardsley@arm.com void 40210259SAndrew.Bardsley@arm.com demapDataPage(Addr vaddr, uint64_t asn) 40310259SAndrew.Bardsley@arm.com { 40410259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 40510259SAndrew.Bardsley@arm.com } 40610259SAndrew.Bardsley@arm.com 40710259SAndrew.Bardsley@arm.com BaseCPU *getCpuPtr() { return &cpu; } 40810259SAndrew.Bardsley@arm.com 40910259SAndrew.Bardsley@arm.com /* MIPS: other thread register reading/writing */ 41013557Sgabeblack@google.com RegVal 41113557Sgabeblack@google.com readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID) 41210259SAndrew.Bardsley@arm.com { 41310259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 41410259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 41510259SAndrew.Bardsley@arm.com 41612106SRekai.GonzalezAlberquilla@arm.com switch (reg.classValue()) { 41712104Snathanael.premillieu@arm.com case IntRegClass: 41812106SRekai.GonzalezAlberquilla@arm.com return other_thread->readIntReg(reg.index()); 41912104Snathanael.premillieu@arm.com break; 42012104Snathanael.premillieu@arm.com case FloatRegClass: 42112106SRekai.GonzalezAlberquilla@arm.com return other_thread->readFloatRegBits(reg.index()); 42212104Snathanael.premillieu@arm.com break; 42312104Snathanael.premillieu@arm.com case MiscRegClass: 42412106SRekai.GonzalezAlberquilla@arm.com return other_thread->readMiscReg(reg.index()); 42512104Snathanael.premillieu@arm.com default: 42612104Snathanael.premillieu@arm.com panic("Unexpected reg class! (%s)", 42712106SRekai.GonzalezAlberquilla@arm.com reg.className()); 42812104Snathanael.premillieu@arm.com return 0; 42910259SAndrew.Bardsley@arm.com } 43010259SAndrew.Bardsley@arm.com } 43110259SAndrew.Bardsley@arm.com 43210259SAndrew.Bardsley@arm.com void 43313582Sgabeblack@google.com setRegOtherThread(const RegId ®, RegVal val, 43413557Sgabeblack@google.com ThreadID tid=InvalidThreadID) 43510259SAndrew.Bardsley@arm.com { 43610259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 43710259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 43810259SAndrew.Bardsley@arm.com 43912106SRekai.GonzalezAlberquilla@arm.com switch (reg.classValue()) { 44012104Snathanael.premillieu@arm.com case IntRegClass: 44112106SRekai.GonzalezAlberquilla@arm.com return other_thread->setIntReg(reg.index(), val); 44212104Snathanael.premillieu@arm.com break; 44312104Snathanael.premillieu@arm.com case FloatRegClass: 44412106SRekai.GonzalezAlberquilla@arm.com return other_thread->setFloatRegBits(reg.index(), val); 44512104Snathanael.premillieu@arm.com break; 44612104Snathanael.premillieu@arm.com case MiscRegClass: 44712106SRekai.GonzalezAlberquilla@arm.com return other_thread->setMiscReg(reg.index(), val); 44812104Snathanael.premillieu@arm.com default: 44912104Snathanael.premillieu@arm.com panic("Unexpected reg class! (%s)", 45012106SRekai.GonzalezAlberquilla@arm.com reg.className()); 45110259SAndrew.Bardsley@arm.com } 45210259SAndrew.Bardsley@arm.com } 45310529Smorr@cs.wisc.edu 45410529Smorr@cs.wisc.edu public: 45510529Smorr@cs.wisc.edu // monitor/mwait funtions 45611611SReiley.Jeyapaul@arm.com void armMonitor(Addr address) override 45711567Smitch.hayenga@arm.com { getCpuPtr()->armMonitor(inst->id.threadId, address); } 45811567Smitch.hayenga@arm.com 45911611SReiley.Jeyapaul@arm.com bool mwait(PacketPtr pkt) override 46011567Smitch.hayenga@arm.com { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 46111567Smitch.hayenga@arm.com 46211611SReiley.Jeyapaul@arm.com void mwaitAtomic(ThreadContext *tc) override 46311567Smitch.hayenga@arm.com { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 46411567Smitch.hayenga@arm.com 46511611SReiley.Jeyapaul@arm.com AddressMonitor *getAddrMonitor() override 46611567Smitch.hayenga@arm.com { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 46710259SAndrew.Bardsley@arm.com}; 46810259SAndrew.Bardsley@arm.com 46910259SAndrew.Bardsley@arm.com} 47010259SAndrew.Bardsley@arm.com 47110259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 472