exec_context.hh revision 12104
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2011-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4310259SAndrew.Bardsley@arm.com * Nathan Binkert 4410259SAndrew.Bardsley@arm.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4910259SAndrew.Bardsley@arm.com * 5010259SAndrew.Bardsley@arm.com * ExecContext bears the exec_context interface for Minor. 5110259SAndrew.Bardsley@arm.com */ 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 6210259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comnamespace Minor 6510259SAndrew.Bardsley@arm.com{ 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6810259SAndrew.Bardsley@arm.comclass Execute; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7110259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7210259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7310259SAndrew.Bardsley@arm.com */ 7410319SAndreas.Sandberg@ARM.comclass ExecContext : public ::ExecContext 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 8010259SAndrew.Bardsley@arm.com SimpleThread &thread; 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8310259SAndrew.Bardsley@arm.com Execute &execute; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8610259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com ExecContext ( 8910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 9010259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9210259SAndrew.Bardsley@arm.com cpu(cpu_), 9310259SAndrew.Bardsley@arm.com thread(thread_), 9410259SAndrew.Bardsley@arm.com execute(execute_), 9510259SAndrew.Bardsley@arm.com inst(inst_) 9610259SAndrew.Bardsley@arm.com { 9710259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9810259SAndrew.Bardsley@arm.com pcState(inst->pc); 9910259SAndrew.Bardsley@arm.com setPredicate(true); 10010259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10110259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10210259SAndrew.Bardsley@arm.com thread.setFloatReg(TheISA::ZeroReg, 0.0); 10310259SAndrew.Bardsley@arm.com#endif 10410259SAndrew.Bardsley@arm.com } 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com Fault 10711612Sandreas.sandberg@arm.com initiateMemRead(Addr addr, unsigned int size, 10811612Sandreas.sandberg@arm.com Request::Flags flags) override 10910259SAndrew.Bardsley@arm.com { 11011303Ssteve.reinhardt@amd.com execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 11110259SAndrew.Bardsley@arm.com size, addr, flags, NULL); 11210259SAndrew.Bardsley@arm.com return NoFault; 11310259SAndrew.Bardsley@arm.com } 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com Fault 11610259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 11711611SReiley.Jeyapaul@arm.com Request::Flags flags, uint64_t *res) override 11810259SAndrew.Bardsley@arm.com { 11910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* store */, data, 12010259SAndrew.Bardsley@arm.com size, addr, flags, res); 12110259SAndrew.Bardsley@arm.com return NoFault; 12210259SAndrew.Bardsley@arm.com } 12310259SAndrew.Bardsley@arm.com 12410319SAndreas.Sandberg@ARM.com IntReg 12511611SReiley.Jeyapaul@arm.com readIntRegOperand(const StaticInst *si, int idx) override 12610259SAndrew.Bardsley@arm.com { 12712104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 12812104Snathanael.premillieu@arm.com assert(reg.regClass == IntRegClass); 12912104Snathanael.premillieu@arm.com return thread.readIntReg(reg.regIdx); 13010259SAndrew.Bardsley@arm.com } 13110259SAndrew.Bardsley@arm.com 13210259SAndrew.Bardsley@arm.com TheISA::FloatReg 13311611SReiley.Jeyapaul@arm.com readFloatRegOperand(const StaticInst *si, int idx) override 13410259SAndrew.Bardsley@arm.com { 13512104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 13612104Snathanael.premillieu@arm.com assert(reg.regClass == FloatRegClass); 13712104Snathanael.premillieu@arm.com return thread.readFloatReg(reg.regIdx); 13810259SAndrew.Bardsley@arm.com } 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com TheISA::FloatRegBits 14111611SReiley.Jeyapaul@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 14210259SAndrew.Bardsley@arm.com { 14312104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 14412104Snathanael.premillieu@arm.com assert(reg.regClass == FloatRegClass); 14512104Snathanael.premillieu@arm.com return thread.readFloatRegBits(reg.regIdx); 14610259SAndrew.Bardsley@arm.com } 14710259SAndrew.Bardsley@arm.com 14810259SAndrew.Bardsley@arm.com void 14911611SReiley.Jeyapaul@arm.com setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 15010259SAndrew.Bardsley@arm.com { 15112104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 15212104Snathanael.premillieu@arm.com assert(reg.regClass == IntRegClass); 15312104Snathanael.premillieu@arm.com thread.setIntReg(reg.regIdx, val); 15410259SAndrew.Bardsley@arm.com } 15510259SAndrew.Bardsley@arm.com 15610259SAndrew.Bardsley@arm.com void 15710259SAndrew.Bardsley@arm.com setFloatRegOperand(const StaticInst *si, int idx, 15811611SReiley.Jeyapaul@arm.com TheISA::FloatReg val) override 15910259SAndrew.Bardsley@arm.com { 16012104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 16112104Snathanael.premillieu@arm.com assert(reg.regClass == FloatRegClass); 16212104Snathanael.premillieu@arm.com thread.setFloatReg(reg.regIdx, val); 16310259SAndrew.Bardsley@arm.com } 16410259SAndrew.Bardsley@arm.com 16510259SAndrew.Bardsley@arm.com void 16610259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, 16711611SReiley.Jeyapaul@arm.com TheISA::FloatRegBits val) override 16810259SAndrew.Bardsley@arm.com { 16912104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 17012104Snathanael.premillieu@arm.com assert(reg.regClass == FloatRegClass); 17112104Snathanael.premillieu@arm.com thread.setFloatRegBits(reg.regIdx, val); 17210259SAndrew.Bardsley@arm.com } 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.com bool 17511611SReiley.Jeyapaul@arm.com readPredicate() override 17610259SAndrew.Bardsley@arm.com { 17710259SAndrew.Bardsley@arm.com return thread.readPredicate(); 17810259SAndrew.Bardsley@arm.com } 17910259SAndrew.Bardsley@arm.com 18010259SAndrew.Bardsley@arm.com void 18111611SReiley.Jeyapaul@arm.com setPredicate(bool val) override 18210259SAndrew.Bardsley@arm.com { 18310259SAndrew.Bardsley@arm.com thread.setPredicate(val); 18410259SAndrew.Bardsley@arm.com } 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.com TheISA::PCState 18711611SReiley.Jeyapaul@arm.com pcState() const override 18810259SAndrew.Bardsley@arm.com { 18910259SAndrew.Bardsley@arm.com return thread.pcState(); 19010259SAndrew.Bardsley@arm.com } 19110259SAndrew.Bardsley@arm.com 19210259SAndrew.Bardsley@arm.com void 19311611SReiley.Jeyapaul@arm.com pcState(const TheISA::PCState &val) override 19410259SAndrew.Bardsley@arm.com { 19510259SAndrew.Bardsley@arm.com thread.pcState(val); 19610259SAndrew.Bardsley@arm.com } 19710259SAndrew.Bardsley@arm.com 19810259SAndrew.Bardsley@arm.com TheISA::MiscReg 19910698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg) const 20010259SAndrew.Bardsley@arm.com { 20110259SAndrew.Bardsley@arm.com return thread.readMiscRegNoEffect(misc_reg); 20210259SAndrew.Bardsley@arm.com } 20310259SAndrew.Bardsley@arm.com 20410259SAndrew.Bardsley@arm.com TheISA::MiscReg 20511611SReiley.Jeyapaul@arm.com readMiscReg(int misc_reg) override 20610259SAndrew.Bardsley@arm.com { 20710259SAndrew.Bardsley@arm.com return thread.readMiscReg(misc_reg); 20810259SAndrew.Bardsley@arm.com } 20910259SAndrew.Bardsley@arm.com 21010259SAndrew.Bardsley@arm.com void 21111611SReiley.Jeyapaul@arm.com setMiscReg(int misc_reg, const TheISA::MiscReg &val) override 21210259SAndrew.Bardsley@arm.com { 21310259SAndrew.Bardsley@arm.com thread.setMiscReg(misc_reg, val); 21410259SAndrew.Bardsley@arm.com } 21510259SAndrew.Bardsley@arm.com 21610259SAndrew.Bardsley@arm.com TheISA::MiscReg 21711611SReiley.Jeyapaul@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 21810259SAndrew.Bardsley@arm.com { 21912104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 22012104Snathanael.premillieu@arm.com assert(reg.regClass == MiscRegClass); 22112104Snathanael.premillieu@arm.com return thread.readMiscReg(reg.regIdx); 22210259SAndrew.Bardsley@arm.com } 22310259SAndrew.Bardsley@arm.com 22410259SAndrew.Bardsley@arm.com void 22510259SAndrew.Bardsley@arm.com setMiscRegOperand(const StaticInst *si, int idx, 22611611SReiley.Jeyapaul@arm.com const TheISA::MiscReg &val) override 22710259SAndrew.Bardsley@arm.com { 22812104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 22912104Snathanael.premillieu@arm.com assert(reg.regClass == MiscRegClass); 23012104Snathanael.premillieu@arm.com return thread.setMiscReg(reg.regIdx, val); 23110259SAndrew.Bardsley@arm.com } 23210259SAndrew.Bardsley@arm.com 23310259SAndrew.Bardsley@arm.com Fault 23411611SReiley.Jeyapaul@arm.com hwrei() override 23510259SAndrew.Bardsley@arm.com { 23610259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 23710259SAndrew.Bardsley@arm.com return thread.hwrei(); 23810259SAndrew.Bardsley@arm.com#else 23910259SAndrew.Bardsley@arm.com return NoFault; 24010259SAndrew.Bardsley@arm.com#endif 24110259SAndrew.Bardsley@arm.com } 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com bool 24411611SReiley.Jeyapaul@arm.com simPalCheck(int palFunc) override 24510259SAndrew.Bardsley@arm.com { 24610259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 24710259SAndrew.Bardsley@arm.com return thread.simPalCheck(palFunc); 24810259SAndrew.Bardsley@arm.com#else 24910259SAndrew.Bardsley@arm.com return false; 25010259SAndrew.Bardsley@arm.com#endif 25110259SAndrew.Bardsley@arm.com } 25210259SAndrew.Bardsley@arm.com 25310259SAndrew.Bardsley@arm.com void 25411877Sbrandon.potter@amd.com syscall(int64_t callnum, Fault *fault) override 25511611SReiley.Jeyapaul@arm.com { 25610259SAndrew.Bardsley@arm.com if (FullSystem) 25710259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode.\n"); 25810259SAndrew.Bardsley@arm.com 25911877Sbrandon.potter@amd.com thread.syscall(callnum, fault); 26010259SAndrew.Bardsley@arm.com } 26110259SAndrew.Bardsley@arm.com 26211611SReiley.Jeyapaul@arm.com ThreadContext *tcBase() override { return thread.getTC(); } 26310259SAndrew.Bardsley@arm.com 26410259SAndrew.Bardsley@arm.com /* @todo, should make stCondFailures persistent somewhere */ 26511611SReiley.Jeyapaul@arm.com unsigned int readStCondFailures() const override { return 0; } 26611611SReiley.Jeyapaul@arm.com void setStCondFailures(unsigned int st_cond_failures) override {} 26710259SAndrew.Bardsley@arm.com 26811005Sandreas.sandberg@arm.com ContextID contextId() { return thread.contextId(); } 26910259SAndrew.Bardsley@arm.com /* ISA-specific (or at least currently ISA singleton) functions */ 27010259SAndrew.Bardsley@arm.com 27110259SAndrew.Bardsley@arm.com /* X86: TLB twiddling */ 27210259SAndrew.Bardsley@arm.com void 27311611SReiley.Jeyapaul@arm.com demapPage(Addr vaddr, uint64_t asn) override 27410259SAndrew.Bardsley@arm.com { 27510259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 27610259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 27710259SAndrew.Bardsley@arm.com } 27810259SAndrew.Bardsley@arm.com 27910935Snilay@cs.wisc.edu TheISA::CCReg 28011611SReiley.Jeyapaul@arm.com readCCRegOperand(const StaticInst *si, int idx) override 28110935Snilay@cs.wisc.edu { 28212104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 28312104Snathanael.premillieu@arm.com assert(reg.regClass == CCRegClass); 28412104Snathanael.premillieu@arm.com return thread.readCCReg(reg.regIdx); 28510935Snilay@cs.wisc.edu } 28610935Snilay@cs.wisc.edu 28710935Snilay@cs.wisc.edu void 28811611SReiley.Jeyapaul@arm.com setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override 28910935Snilay@cs.wisc.edu { 29012104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 29112104Snathanael.premillieu@arm.com assert(reg.regClass == CCRegClass); 29212104Snathanael.premillieu@arm.com thread.setCCReg(reg.regIdx, val); 29310935Snilay@cs.wisc.edu } 29410935Snilay@cs.wisc.edu 29510259SAndrew.Bardsley@arm.com void 29610259SAndrew.Bardsley@arm.com demapInstPage(Addr vaddr, uint64_t asn) 29710259SAndrew.Bardsley@arm.com { 29810259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 29910259SAndrew.Bardsley@arm.com } 30010259SAndrew.Bardsley@arm.com 30110259SAndrew.Bardsley@arm.com void 30210259SAndrew.Bardsley@arm.com demapDataPage(Addr vaddr, uint64_t asn) 30310259SAndrew.Bardsley@arm.com { 30410259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 30510259SAndrew.Bardsley@arm.com } 30610259SAndrew.Bardsley@arm.com 30710259SAndrew.Bardsley@arm.com /* ALPHA/POWER: Effective address storage */ 30811611SReiley.Jeyapaul@arm.com void setEA(Addr ea) override 30910259SAndrew.Bardsley@arm.com { 31010259SAndrew.Bardsley@arm.com inst->ea = ea; 31110259SAndrew.Bardsley@arm.com } 31210259SAndrew.Bardsley@arm.com 31310259SAndrew.Bardsley@arm.com BaseCPU *getCpuPtr() { return &cpu; } 31410259SAndrew.Bardsley@arm.com 31510259SAndrew.Bardsley@arm.com /* POWER: Effective address storage */ 31611611SReiley.Jeyapaul@arm.com Addr getEA() const override 31710259SAndrew.Bardsley@arm.com { 31810259SAndrew.Bardsley@arm.com return inst->ea; 31910259SAndrew.Bardsley@arm.com } 32010259SAndrew.Bardsley@arm.com 32110259SAndrew.Bardsley@arm.com /* MIPS: other thread register reading/writing */ 32210259SAndrew.Bardsley@arm.com uint64_t 32312104Snathanael.premillieu@arm.com readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID) 32410259SAndrew.Bardsley@arm.com { 32510259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 32610259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 32710259SAndrew.Bardsley@arm.com 32812104Snathanael.premillieu@arm.com switch(reg.regClass) { 32912104Snathanael.premillieu@arm.com case IntRegClass: 33012104Snathanael.premillieu@arm.com return other_thread->readIntReg(reg.regIdx); 33112104Snathanael.premillieu@arm.com break; 33212104Snathanael.premillieu@arm.com case FloatRegClass: 33312104Snathanael.premillieu@arm.com return other_thread->readFloatRegBits(reg.regIdx); 33412104Snathanael.premillieu@arm.com break; 33512104Snathanael.premillieu@arm.com case MiscRegClass: 33612104Snathanael.premillieu@arm.com return other_thread->readMiscReg(reg.regIdx); 33712104Snathanael.premillieu@arm.com default: 33812104Snathanael.premillieu@arm.com panic("Unexpected reg class! (%s)", 33912104Snathanael.premillieu@arm.com RegClassStrings[reg.regClass]); 34012104Snathanael.premillieu@arm.com return 0; 34110259SAndrew.Bardsley@arm.com } 34210259SAndrew.Bardsley@arm.com } 34310259SAndrew.Bardsley@arm.com 34410259SAndrew.Bardsley@arm.com void 34512104Snathanael.premillieu@arm.com setRegOtherThread(RegId reg, const TheISA::MiscReg &val, 34610259SAndrew.Bardsley@arm.com ThreadID tid = InvalidThreadID) 34710259SAndrew.Bardsley@arm.com { 34810259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 34910259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 35010259SAndrew.Bardsley@arm.com 35112104Snathanael.premillieu@arm.com switch(reg.regClass) { 35212104Snathanael.premillieu@arm.com case IntRegClass: 35312104Snathanael.premillieu@arm.com return other_thread->setIntReg(reg.regIdx, val); 35412104Snathanael.premillieu@arm.com break; 35512104Snathanael.premillieu@arm.com case FloatRegClass: 35612104Snathanael.premillieu@arm.com return other_thread->setFloatRegBits(reg.regIdx, val); 35712104Snathanael.premillieu@arm.com break; 35812104Snathanael.premillieu@arm.com case MiscRegClass: 35912104Snathanael.premillieu@arm.com return other_thread->setMiscReg(reg.regIdx, val); 36012104Snathanael.premillieu@arm.com default: 36112104Snathanael.premillieu@arm.com panic("Unexpected reg class! (%s)", 36212104Snathanael.premillieu@arm.com RegClassStrings[reg.regClass]); 36310259SAndrew.Bardsley@arm.com } 36410259SAndrew.Bardsley@arm.com } 36510529Smorr@cs.wisc.edu 36610529Smorr@cs.wisc.edu public: 36710529Smorr@cs.wisc.edu // monitor/mwait funtions 36811611SReiley.Jeyapaul@arm.com void armMonitor(Addr address) override 36911567Smitch.hayenga@arm.com { getCpuPtr()->armMonitor(inst->id.threadId, address); } 37011567Smitch.hayenga@arm.com 37111611SReiley.Jeyapaul@arm.com bool mwait(PacketPtr pkt) override 37211567Smitch.hayenga@arm.com { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 37311567Smitch.hayenga@arm.com 37411611SReiley.Jeyapaul@arm.com void mwaitAtomic(ThreadContext *tc) override 37511567Smitch.hayenga@arm.com { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 37611567Smitch.hayenga@arm.com 37711611SReiley.Jeyapaul@arm.com AddressMonitor *getAddrMonitor() override 37811567Smitch.hayenga@arm.com { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 37910259SAndrew.Bardsley@arm.com}; 38010259SAndrew.Bardsley@arm.com 38110259SAndrew.Bardsley@arm.com} 38210259SAndrew.Bardsley@arm.com 38310259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 384