exec_context.hh revision 11303
110259SAndrew.Bardsley@arm.com/*
210259SAndrew.Bardsley@arm.com * Copyright (c) 2011-2014 ARM Limited
310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
410259SAndrew.Bardsley@arm.com * All rights reserved
510259SAndrew.Bardsley@arm.com *
610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall
710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual
810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating
910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software
1010259SAndrew.Bardsley@arm.com * licensed hereunder.  You may use the software subject to the license
1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated
1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software,
1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form.
1410259SAndrew.Bardsley@arm.com *
1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
1610259SAndrew.Bardsley@arm.com * All rights reserved.
1710259SAndrew.Bardsley@arm.com *
1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without
1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are
2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright
2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer;
2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright
2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the
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2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission.
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2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4010259SAndrew.Bardsley@arm.com *
4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt
4210259SAndrew.Bardsley@arm.com *          Dave Greene
4310259SAndrew.Bardsley@arm.com *          Nathan Binkert
4410259SAndrew.Bardsley@arm.com *          Andrew Bardsley
4510259SAndrew.Bardsley@arm.com */
4610259SAndrew.Bardsley@arm.com
4710259SAndrew.Bardsley@arm.com/**
4810259SAndrew.Bardsley@arm.com * @file
4910259SAndrew.Bardsley@arm.com *
5010259SAndrew.Bardsley@arm.com *  ExecContext bears the exec_context interface for Minor.
5110259SAndrew.Bardsley@arm.com */
5210259SAndrew.Bardsley@arm.com
5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__
5510259SAndrew.Bardsley@arm.com
5610319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh"
5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh"
5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh"
5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh"
6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh"
6110259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh"
6210259SAndrew.Bardsley@arm.com
6310259SAndrew.Bardsley@arm.comnamespace Minor
6410259SAndrew.Bardsley@arm.com{
6510259SAndrew.Bardsley@arm.com
6610259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */
6710259SAndrew.Bardsley@arm.comclass Execute;
6810259SAndrew.Bardsley@arm.com
6910259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor.  This nicely
7010259SAndrew.Bardsley@arm.com *  separates that interface from other classes such as Pipeline, MinorCPU
7110259SAndrew.Bardsley@arm.com *  and DynMinorInst and makes it easier to see what state is accessed by it.
7210259SAndrew.Bardsley@arm.com */
7310319SAndreas.Sandberg@ARM.comclass ExecContext : public ::ExecContext
7410259SAndrew.Bardsley@arm.com{
7510259SAndrew.Bardsley@arm.com  public:
7610259SAndrew.Bardsley@arm.com    MinorCPU &cpu;
7710259SAndrew.Bardsley@arm.com
7810259SAndrew.Bardsley@arm.com    /** ThreadState object, provides all the architectural state. */
7910259SAndrew.Bardsley@arm.com    SimpleThread &thread;
8010259SAndrew.Bardsley@arm.com
8110259SAndrew.Bardsley@arm.com    /** The execute stage so we can peek at its contents. */
8210259SAndrew.Bardsley@arm.com    Execute &execute;
8310259SAndrew.Bardsley@arm.com
8410259SAndrew.Bardsley@arm.com    /** Instruction for the benefit of memory operations and for PC */
8510259SAndrew.Bardsley@arm.com    MinorDynInstPtr inst;
8610259SAndrew.Bardsley@arm.com
8710259SAndrew.Bardsley@arm.com    ExecContext (
8810259SAndrew.Bardsley@arm.com        MinorCPU &cpu_,
8910259SAndrew.Bardsley@arm.com        SimpleThread &thread_, Execute &execute_,
9010259SAndrew.Bardsley@arm.com        MinorDynInstPtr inst_) :
9110259SAndrew.Bardsley@arm.com        cpu(cpu_),
9210259SAndrew.Bardsley@arm.com        thread(thread_),
9310259SAndrew.Bardsley@arm.com        execute(execute_),
9410259SAndrew.Bardsley@arm.com        inst(inst_)
9510259SAndrew.Bardsley@arm.com    {
9610259SAndrew.Bardsley@arm.com        DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
9710259SAndrew.Bardsley@arm.com        pcState(inst->pc);
9810259SAndrew.Bardsley@arm.com        setPredicate(true);
9910259SAndrew.Bardsley@arm.com        thread.setIntReg(TheISA::ZeroReg, 0);
10010259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA
10110259SAndrew.Bardsley@arm.com        thread.setFloatReg(TheISA::ZeroReg, 0.0);
10210259SAndrew.Bardsley@arm.com#endif
10310259SAndrew.Bardsley@arm.com    }
10410259SAndrew.Bardsley@arm.com
10510259SAndrew.Bardsley@arm.com    Fault
10611303Ssteve.reinhardt@amd.com    initiateMemRead(Addr addr, unsigned int size, unsigned int flags)
10710259SAndrew.Bardsley@arm.com    {
10811303Ssteve.reinhardt@amd.com        execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
10910259SAndrew.Bardsley@arm.com            size, addr, flags, NULL);
11010259SAndrew.Bardsley@arm.com        return NoFault;
11110259SAndrew.Bardsley@arm.com    }
11210259SAndrew.Bardsley@arm.com
11310259SAndrew.Bardsley@arm.com    Fault
11410259SAndrew.Bardsley@arm.com    writeMem(uint8_t *data, unsigned int size, Addr addr,
11510259SAndrew.Bardsley@arm.com        unsigned int flags, uint64_t *res)
11610259SAndrew.Bardsley@arm.com    {
11710259SAndrew.Bardsley@arm.com        execute.getLSQ().pushRequest(inst, false /* store */, data,
11810259SAndrew.Bardsley@arm.com            size, addr, flags, res);
11910259SAndrew.Bardsley@arm.com        return NoFault;
12010259SAndrew.Bardsley@arm.com    }
12110259SAndrew.Bardsley@arm.com
12210319SAndreas.Sandberg@ARM.com    IntReg
12310259SAndrew.Bardsley@arm.com    readIntRegOperand(const StaticInst *si, int idx)
12410259SAndrew.Bardsley@arm.com    {
12510259SAndrew.Bardsley@arm.com        return thread.readIntReg(si->srcRegIdx(idx));
12610259SAndrew.Bardsley@arm.com    }
12710259SAndrew.Bardsley@arm.com
12810259SAndrew.Bardsley@arm.com    TheISA::FloatReg
12910259SAndrew.Bardsley@arm.com    readFloatRegOperand(const StaticInst *si, int idx)
13010259SAndrew.Bardsley@arm.com    {
13110259SAndrew.Bardsley@arm.com        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
13210259SAndrew.Bardsley@arm.com        return thread.readFloatReg(reg_idx);
13310259SAndrew.Bardsley@arm.com    }
13410259SAndrew.Bardsley@arm.com
13510259SAndrew.Bardsley@arm.com    TheISA::FloatRegBits
13610259SAndrew.Bardsley@arm.com    readFloatRegOperandBits(const StaticInst *si, int idx)
13710259SAndrew.Bardsley@arm.com    {
13810259SAndrew.Bardsley@arm.com        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
13910259SAndrew.Bardsley@arm.com        return thread.readFloatRegBits(reg_idx);
14010259SAndrew.Bardsley@arm.com    }
14110259SAndrew.Bardsley@arm.com
14210259SAndrew.Bardsley@arm.com    void
14310319SAndreas.Sandberg@ARM.com    setIntRegOperand(const StaticInst *si, int idx, IntReg val)
14410259SAndrew.Bardsley@arm.com    {
14510259SAndrew.Bardsley@arm.com        thread.setIntReg(si->destRegIdx(idx), val);
14610259SAndrew.Bardsley@arm.com    }
14710259SAndrew.Bardsley@arm.com
14810259SAndrew.Bardsley@arm.com    void
14910259SAndrew.Bardsley@arm.com    setFloatRegOperand(const StaticInst *si, int idx,
15010259SAndrew.Bardsley@arm.com        TheISA::FloatReg val)
15110259SAndrew.Bardsley@arm.com    {
15210259SAndrew.Bardsley@arm.com        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
15310259SAndrew.Bardsley@arm.com        thread.setFloatReg(reg_idx, val);
15410259SAndrew.Bardsley@arm.com    }
15510259SAndrew.Bardsley@arm.com
15610259SAndrew.Bardsley@arm.com    void
15710259SAndrew.Bardsley@arm.com    setFloatRegOperandBits(const StaticInst *si, int idx,
15810259SAndrew.Bardsley@arm.com        TheISA::FloatRegBits val)
15910259SAndrew.Bardsley@arm.com    {
16010259SAndrew.Bardsley@arm.com        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
16110259SAndrew.Bardsley@arm.com        thread.setFloatRegBits(reg_idx, val);
16210259SAndrew.Bardsley@arm.com    }
16310259SAndrew.Bardsley@arm.com
16410259SAndrew.Bardsley@arm.com    bool
16510259SAndrew.Bardsley@arm.com    readPredicate()
16610259SAndrew.Bardsley@arm.com    {
16710259SAndrew.Bardsley@arm.com        return thread.readPredicate();
16810259SAndrew.Bardsley@arm.com    }
16910259SAndrew.Bardsley@arm.com
17010259SAndrew.Bardsley@arm.com    void
17110259SAndrew.Bardsley@arm.com    setPredicate(bool val)
17210259SAndrew.Bardsley@arm.com    {
17310259SAndrew.Bardsley@arm.com        thread.setPredicate(val);
17410259SAndrew.Bardsley@arm.com    }
17510259SAndrew.Bardsley@arm.com
17610259SAndrew.Bardsley@arm.com    TheISA::PCState
17710319SAndreas.Sandberg@ARM.com    pcState() const
17810259SAndrew.Bardsley@arm.com    {
17910259SAndrew.Bardsley@arm.com        return thread.pcState();
18010259SAndrew.Bardsley@arm.com    }
18110259SAndrew.Bardsley@arm.com
18210259SAndrew.Bardsley@arm.com    void
18310259SAndrew.Bardsley@arm.com    pcState(const TheISA::PCState &val)
18410259SAndrew.Bardsley@arm.com    {
18510259SAndrew.Bardsley@arm.com        thread.pcState(val);
18610259SAndrew.Bardsley@arm.com    }
18710259SAndrew.Bardsley@arm.com
18810259SAndrew.Bardsley@arm.com    TheISA::MiscReg
18910698Sandreas.hansson@arm.com    readMiscRegNoEffect(int misc_reg) const
19010259SAndrew.Bardsley@arm.com    {
19110259SAndrew.Bardsley@arm.com        return thread.readMiscRegNoEffect(misc_reg);
19210259SAndrew.Bardsley@arm.com    }
19310259SAndrew.Bardsley@arm.com
19410259SAndrew.Bardsley@arm.com    TheISA::MiscReg
19510259SAndrew.Bardsley@arm.com    readMiscReg(int misc_reg)
19610259SAndrew.Bardsley@arm.com    {
19710259SAndrew.Bardsley@arm.com        return thread.readMiscReg(misc_reg);
19810259SAndrew.Bardsley@arm.com    }
19910259SAndrew.Bardsley@arm.com
20010259SAndrew.Bardsley@arm.com    void
20110259SAndrew.Bardsley@arm.com    setMiscReg(int misc_reg, const TheISA::MiscReg &val)
20210259SAndrew.Bardsley@arm.com    {
20310259SAndrew.Bardsley@arm.com        thread.setMiscReg(misc_reg, val);
20410259SAndrew.Bardsley@arm.com    }
20510259SAndrew.Bardsley@arm.com
20610259SAndrew.Bardsley@arm.com    TheISA::MiscReg
20710259SAndrew.Bardsley@arm.com    readMiscRegOperand(const StaticInst *si, int idx)
20810259SAndrew.Bardsley@arm.com    {
20910259SAndrew.Bardsley@arm.com        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
21010259SAndrew.Bardsley@arm.com        return thread.readMiscReg(reg_idx);
21110259SAndrew.Bardsley@arm.com    }
21210259SAndrew.Bardsley@arm.com
21310259SAndrew.Bardsley@arm.com    void
21410259SAndrew.Bardsley@arm.com    setMiscRegOperand(const StaticInst *si, int idx,
21510259SAndrew.Bardsley@arm.com        const TheISA::MiscReg &val)
21610259SAndrew.Bardsley@arm.com    {
21710259SAndrew.Bardsley@arm.com        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
21810259SAndrew.Bardsley@arm.com        return thread.setMiscReg(reg_idx, val);
21910259SAndrew.Bardsley@arm.com    }
22010259SAndrew.Bardsley@arm.com
22110259SAndrew.Bardsley@arm.com    Fault
22210259SAndrew.Bardsley@arm.com    hwrei()
22310259SAndrew.Bardsley@arm.com    {
22410259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA
22510259SAndrew.Bardsley@arm.com        return thread.hwrei();
22610259SAndrew.Bardsley@arm.com#else
22710259SAndrew.Bardsley@arm.com        return NoFault;
22810259SAndrew.Bardsley@arm.com#endif
22910259SAndrew.Bardsley@arm.com    }
23010259SAndrew.Bardsley@arm.com
23110259SAndrew.Bardsley@arm.com    bool
23210259SAndrew.Bardsley@arm.com    simPalCheck(int palFunc)
23310259SAndrew.Bardsley@arm.com    {
23410259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA
23510259SAndrew.Bardsley@arm.com        return thread.simPalCheck(palFunc);
23610259SAndrew.Bardsley@arm.com#else
23710259SAndrew.Bardsley@arm.com        return false;
23810259SAndrew.Bardsley@arm.com#endif
23910259SAndrew.Bardsley@arm.com    }
24010259SAndrew.Bardsley@arm.com
24110259SAndrew.Bardsley@arm.com    void
24210259SAndrew.Bardsley@arm.com    syscall(int64_t callnum)
24310259SAndrew.Bardsley@arm.com    {
24410259SAndrew.Bardsley@arm.com        if (FullSystem)
24510259SAndrew.Bardsley@arm.com            panic("Syscall emulation isn't available in FS mode.\n");
24610259SAndrew.Bardsley@arm.com
24710259SAndrew.Bardsley@arm.com        thread.syscall(callnum);
24810259SAndrew.Bardsley@arm.com    }
24910259SAndrew.Bardsley@arm.com
25010259SAndrew.Bardsley@arm.com    ThreadContext *tcBase() { return thread.getTC(); }
25110259SAndrew.Bardsley@arm.com
25210259SAndrew.Bardsley@arm.com    /* @todo, should make stCondFailures persistent somewhere */
25310319SAndreas.Sandberg@ARM.com    unsigned int readStCondFailures() const { return 0; }
25410319SAndreas.Sandberg@ARM.com    void setStCondFailures(unsigned int st_cond_failures) {}
25510259SAndrew.Bardsley@arm.com
25611005Sandreas.sandberg@arm.com    ContextID contextId() { return thread.contextId(); }
25710259SAndrew.Bardsley@arm.com    /* ISA-specific (or at least currently ISA singleton) functions */
25810259SAndrew.Bardsley@arm.com
25910259SAndrew.Bardsley@arm.com    /* X86: TLB twiddling */
26010259SAndrew.Bardsley@arm.com    void
26110259SAndrew.Bardsley@arm.com    demapPage(Addr vaddr, uint64_t asn)
26210259SAndrew.Bardsley@arm.com    {
26310259SAndrew.Bardsley@arm.com        thread.getITBPtr()->demapPage(vaddr, asn);
26410259SAndrew.Bardsley@arm.com        thread.getDTBPtr()->demapPage(vaddr, asn);
26510259SAndrew.Bardsley@arm.com    }
26610259SAndrew.Bardsley@arm.com
26710935Snilay@cs.wisc.edu    TheISA::CCReg
26810935Snilay@cs.wisc.edu    readCCRegOperand(const StaticInst *si, int idx)
26910935Snilay@cs.wisc.edu    {
27010935Snilay@cs.wisc.edu        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
27110935Snilay@cs.wisc.edu        return thread.readCCReg(reg_idx);
27210935Snilay@cs.wisc.edu    }
27310935Snilay@cs.wisc.edu
27410935Snilay@cs.wisc.edu    void
27510935Snilay@cs.wisc.edu    setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
27610935Snilay@cs.wisc.edu    {
27710935Snilay@cs.wisc.edu        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
27810935Snilay@cs.wisc.edu        thread.setCCReg(reg_idx, val);
27910935Snilay@cs.wisc.edu    }
28010935Snilay@cs.wisc.edu
28110259SAndrew.Bardsley@arm.com    void
28210259SAndrew.Bardsley@arm.com    demapInstPage(Addr vaddr, uint64_t asn)
28310259SAndrew.Bardsley@arm.com    {
28410259SAndrew.Bardsley@arm.com        thread.getITBPtr()->demapPage(vaddr, asn);
28510259SAndrew.Bardsley@arm.com    }
28610259SAndrew.Bardsley@arm.com
28710259SAndrew.Bardsley@arm.com    void
28810259SAndrew.Bardsley@arm.com    demapDataPage(Addr vaddr, uint64_t asn)
28910259SAndrew.Bardsley@arm.com    {
29010259SAndrew.Bardsley@arm.com        thread.getDTBPtr()->demapPage(vaddr, asn);
29110259SAndrew.Bardsley@arm.com    }
29210259SAndrew.Bardsley@arm.com
29310259SAndrew.Bardsley@arm.com    /* ALPHA/POWER: Effective address storage */
29410319SAndreas.Sandberg@ARM.com    void setEA(Addr ea)
29510259SAndrew.Bardsley@arm.com    {
29610259SAndrew.Bardsley@arm.com        inst->ea = ea;
29710259SAndrew.Bardsley@arm.com    }
29810259SAndrew.Bardsley@arm.com
29910259SAndrew.Bardsley@arm.com    BaseCPU *getCpuPtr() { return &cpu; }
30010259SAndrew.Bardsley@arm.com
30110259SAndrew.Bardsley@arm.com    /* POWER: Effective address storage */
30210319SAndreas.Sandberg@ARM.com    Addr getEA() const
30310259SAndrew.Bardsley@arm.com    {
30410259SAndrew.Bardsley@arm.com        return inst->ea;
30510259SAndrew.Bardsley@arm.com    }
30610259SAndrew.Bardsley@arm.com
30710259SAndrew.Bardsley@arm.com    /* MIPS: other thread register reading/writing */
30810259SAndrew.Bardsley@arm.com    uint64_t
30910319SAndreas.Sandberg@ARM.com    readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
31010259SAndrew.Bardsley@arm.com    {
31110259SAndrew.Bardsley@arm.com        SimpleThread *other_thread = (tid == InvalidThreadID
31210259SAndrew.Bardsley@arm.com            ? &thread : cpu.threads[tid]);
31310259SAndrew.Bardsley@arm.com
31410259SAndrew.Bardsley@arm.com        if (idx < TheISA::FP_Reg_Base) { /* Integer */
31510259SAndrew.Bardsley@arm.com            return other_thread->readIntReg(idx);
31610259SAndrew.Bardsley@arm.com        } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
31710259SAndrew.Bardsley@arm.com            return other_thread->readFloatRegBits(idx
31810259SAndrew.Bardsley@arm.com                - TheISA::FP_Reg_Base);
31910259SAndrew.Bardsley@arm.com        } else { /* Misc */
32010259SAndrew.Bardsley@arm.com            return other_thread->readMiscReg(idx
32110259SAndrew.Bardsley@arm.com                - TheISA::Misc_Reg_Base);
32210259SAndrew.Bardsley@arm.com        }
32310259SAndrew.Bardsley@arm.com    }
32410259SAndrew.Bardsley@arm.com
32510259SAndrew.Bardsley@arm.com    void
32610319SAndreas.Sandberg@ARM.com    setRegOtherThread(int idx, const TheISA::MiscReg &val,
32710259SAndrew.Bardsley@arm.com        ThreadID tid = InvalidThreadID)
32810259SAndrew.Bardsley@arm.com    {
32910259SAndrew.Bardsley@arm.com        SimpleThread *other_thread = (tid == InvalidThreadID
33010259SAndrew.Bardsley@arm.com            ? &thread : cpu.threads[tid]);
33110259SAndrew.Bardsley@arm.com
33210259SAndrew.Bardsley@arm.com        if (idx < TheISA::FP_Reg_Base) { /* Integer */
33310259SAndrew.Bardsley@arm.com            return other_thread->setIntReg(idx, val);
33410259SAndrew.Bardsley@arm.com        } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
33510259SAndrew.Bardsley@arm.com            return other_thread->setFloatRegBits(idx
33610259SAndrew.Bardsley@arm.com                - TheISA::FP_Reg_Base, val);
33710259SAndrew.Bardsley@arm.com        } else { /* Misc */
33810259SAndrew.Bardsley@arm.com            return other_thread->setMiscReg(idx
33910259SAndrew.Bardsley@arm.com                - TheISA::Misc_Reg_Base, val);
34010259SAndrew.Bardsley@arm.com        }
34110259SAndrew.Bardsley@arm.com    }
34210529Smorr@cs.wisc.edu
34310529Smorr@cs.wisc.edu  public:
34410529Smorr@cs.wisc.edu    // monitor/mwait funtions
34511148Smitch.hayenga@arm.com    void armMonitor(Addr address) { getCpuPtr()->armMonitor(0, address); }
34611148Smitch.hayenga@arm.com    bool mwait(PacketPtr pkt) { return getCpuPtr()->mwait(0, pkt); }
34710529Smorr@cs.wisc.edu    void mwaitAtomic(ThreadContext *tc)
34811148Smitch.hayenga@arm.com    { return getCpuPtr()->mwaitAtomic(0, tc, thread.dtb); }
34910529Smorr@cs.wisc.edu    AddressMonitor *getAddrMonitor()
35011148Smitch.hayenga@arm.com    { return getCpuPtr()->getCpuAddrMonitor(0); }
35110259SAndrew.Bardsley@arm.com};
35210259SAndrew.Bardsley@arm.com
35310259SAndrew.Bardsley@arm.com}
35410259SAndrew.Bardsley@arm.com
35510259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
356