exec_context.hh revision 10529
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2011-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4310259SAndrew.Bardsley@arm.com * Nathan Binkert 4410259SAndrew.Bardsley@arm.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4910259SAndrew.Bardsley@arm.com * 5010259SAndrew.Bardsley@arm.com * ExecContext bears the exec_context interface for Minor. 5110259SAndrew.Bardsley@arm.com */ 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6110259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.comnamespace Minor 6410259SAndrew.Bardsley@arm.com{ 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6710259SAndrew.Bardsley@arm.comclass Execute; 6810259SAndrew.Bardsley@arm.com 6910259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7010259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7110259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7210259SAndrew.Bardsley@arm.com */ 7310319SAndreas.Sandberg@ARM.comclass ExecContext : public ::ExecContext 7410259SAndrew.Bardsley@arm.com{ 7510259SAndrew.Bardsley@arm.com public: 7610259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 7910259SAndrew.Bardsley@arm.com SimpleThread &thread; 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8210259SAndrew.Bardsley@arm.com Execute &execute; 8310259SAndrew.Bardsley@arm.com 8410259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8510259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8610259SAndrew.Bardsley@arm.com 8710259SAndrew.Bardsley@arm.com ExecContext ( 8810259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 8910259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9010259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9110259SAndrew.Bardsley@arm.com cpu(cpu_), 9210259SAndrew.Bardsley@arm.com thread(thread_), 9310259SAndrew.Bardsley@arm.com execute(execute_), 9410259SAndrew.Bardsley@arm.com inst(inst_) 9510259SAndrew.Bardsley@arm.com { 9610259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9710259SAndrew.Bardsley@arm.com pcState(inst->pc); 9810259SAndrew.Bardsley@arm.com setPredicate(true); 9910259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10010259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10110259SAndrew.Bardsley@arm.com thread.setFloatReg(TheISA::ZeroReg, 0.0); 10210259SAndrew.Bardsley@arm.com#endif 10310259SAndrew.Bardsley@arm.com } 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.com Fault 10610259SAndrew.Bardsley@arm.com readMem(Addr addr, uint8_t *data, unsigned int size, 10710259SAndrew.Bardsley@arm.com unsigned int flags) 10810259SAndrew.Bardsley@arm.com { 10910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, true /* load */, data, 11010259SAndrew.Bardsley@arm.com size, addr, flags, NULL); 11110259SAndrew.Bardsley@arm.com return NoFault; 11210259SAndrew.Bardsley@arm.com } 11310259SAndrew.Bardsley@arm.com 11410259SAndrew.Bardsley@arm.com Fault 11510259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 11610259SAndrew.Bardsley@arm.com unsigned int flags, uint64_t *res) 11710259SAndrew.Bardsley@arm.com { 11810259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* store */, data, 11910259SAndrew.Bardsley@arm.com size, addr, flags, res); 12010259SAndrew.Bardsley@arm.com return NoFault; 12110259SAndrew.Bardsley@arm.com } 12210259SAndrew.Bardsley@arm.com 12310319SAndreas.Sandberg@ARM.com IntReg 12410259SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) 12510259SAndrew.Bardsley@arm.com { 12610259SAndrew.Bardsley@arm.com return thread.readIntReg(si->srcRegIdx(idx)); 12710259SAndrew.Bardsley@arm.com } 12810259SAndrew.Bardsley@arm.com 12910259SAndrew.Bardsley@arm.com TheISA::FloatReg 13010259SAndrew.Bardsley@arm.com readFloatRegOperand(const StaticInst *si, int idx) 13110259SAndrew.Bardsley@arm.com { 13210259SAndrew.Bardsley@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 13310259SAndrew.Bardsley@arm.com return thread.readFloatReg(reg_idx); 13410259SAndrew.Bardsley@arm.com } 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com TheISA::FloatRegBits 13710259SAndrew.Bardsley@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) 13810259SAndrew.Bardsley@arm.com { 13910259SAndrew.Bardsley@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 14010259SAndrew.Bardsley@arm.com return thread.readFloatRegBits(reg_idx); 14110259SAndrew.Bardsley@arm.com } 14210259SAndrew.Bardsley@arm.com 14310259SAndrew.Bardsley@arm.com void 14410319SAndreas.Sandberg@ARM.com setIntRegOperand(const StaticInst *si, int idx, IntReg val) 14510259SAndrew.Bardsley@arm.com { 14610259SAndrew.Bardsley@arm.com thread.setIntReg(si->destRegIdx(idx), val); 14710259SAndrew.Bardsley@arm.com } 14810259SAndrew.Bardsley@arm.com 14910259SAndrew.Bardsley@arm.com void 15010259SAndrew.Bardsley@arm.com setFloatRegOperand(const StaticInst *si, int idx, 15110259SAndrew.Bardsley@arm.com TheISA::FloatReg val) 15210259SAndrew.Bardsley@arm.com { 15310259SAndrew.Bardsley@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 15410259SAndrew.Bardsley@arm.com thread.setFloatReg(reg_idx, val); 15510259SAndrew.Bardsley@arm.com } 15610259SAndrew.Bardsley@arm.com 15710259SAndrew.Bardsley@arm.com void 15810259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, 15910259SAndrew.Bardsley@arm.com TheISA::FloatRegBits val) 16010259SAndrew.Bardsley@arm.com { 16110259SAndrew.Bardsley@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 16210259SAndrew.Bardsley@arm.com thread.setFloatRegBits(reg_idx, val); 16310259SAndrew.Bardsley@arm.com } 16410259SAndrew.Bardsley@arm.com 16510259SAndrew.Bardsley@arm.com bool 16610259SAndrew.Bardsley@arm.com readPredicate() 16710259SAndrew.Bardsley@arm.com { 16810259SAndrew.Bardsley@arm.com return thread.readPredicate(); 16910259SAndrew.Bardsley@arm.com } 17010259SAndrew.Bardsley@arm.com 17110259SAndrew.Bardsley@arm.com void 17210259SAndrew.Bardsley@arm.com setPredicate(bool val) 17310259SAndrew.Bardsley@arm.com { 17410259SAndrew.Bardsley@arm.com thread.setPredicate(val); 17510259SAndrew.Bardsley@arm.com } 17610259SAndrew.Bardsley@arm.com 17710259SAndrew.Bardsley@arm.com TheISA::PCState 17810319SAndreas.Sandberg@ARM.com pcState() const 17910259SAndrew.Bardsley@arm.com { 18010259SAndrew.Bardsley@arm.com return thread.pcState(); 18110259SAndrew.Bardsley@arm.com } 18210259SAndrew.Bardsley@arm.com 18310259SAndrew.Bardsley@arm.com void 18410259SAndrew.Bardsley@arm.com pcState(const TheISA::PCState &val) 18510259SAndrew.Bardsley@arm.com { 18610259SAndrew.Bardsley@arm.com thread.pcState(val); 18710259SAndrew.Bardsley@arm.com } 18810259SAndrew.Bardsley@arm.com 18910259SAndrew.Bardsley@arm.com TheISA::MiscReg 19010259SAndrew.Bardsley@arm.com readMiscRegNoEffect(int misc_reg) 19110259SAndrew.Bardsley@arm.com { 19210259SAndrew.Bardsley@arm.com return thread.readMiscRegNoEffect(misc_reg); 19310259SAndrew.Bardsley@arm.com } 19410259SAndrew.Bardsley@arm.com 19510259SAndrew.Bardsley@arm.com TheISA::MiscReg 19610259SAndrew.Bardsley@arm.com readMiscReg(int misc_reg) 19710259SAndrew.Bardsley@arm.com { 19810259SAndrew.Bardsley@arm.com return thread.readMiscReg(misc_reg); 19910259SAndrew.Bardsley@arm.com } 20010259SAndrew.Bardsley@arm.com 20110259SAndrew.Bardsley@arm.com void 20210259SAndrew.Bardsley@arm.com setMiscReg(int misc_reg, const TheISA::MiscReg &val) 20310259SAndrew.Bardsley@arm.com { 20410259SAndrew.Bardsley@arm.com thread.setMiscReg(misc_reg, val); 20510259SAndrew.Bardsley@arm.com } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com TheISA::MiscReg 20810259SAndrew.Bardsley@arm.com readMiscRegOperand(const StaticInst *si, int idx) 20910259SAndrew.Bardsley@arm.com { 21010259SAndrew.Bardsley@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 21110259SAndrew.Bardsley@arm.com return thread.readMiscReg(reg_idx); 21210259SAndrew.Bardsley@arm.com } 21310259SAndrew.Bardsley@arm.com 21410259SAndrew.Bardsley@arm.com void 21510259SAndrew.Bardsley@arm.com setMiscRegOperand(const StaticInst *si, int idx, 21610259SAndrew.Bardsley@arm.com const TheISA::MiscReg &val) 21710259SAndrew.Bardsley@arm.com { 21810259SAndrew.Bardsley@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 21910259SAndrew.Bardsley@arm.com return thread.setMiscReg(reg_idx, val); 22010259SAndrew.Bardsley@arm.com } 22110259SAndrew.Bardsley@arm.com 22210259SAndrew.Bardsley@arm.com Fault 22310259SAndrew.Bardsley@arm.com hwrei() 22410259SAndrew.Bardsley@arm.com { 22510259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 22610259SAndrew.Bardsley@arm.com return thread.hwrei(); 22710259SAndrew.Bardsley@arm.com#else 22810259SAndrew.Bardsley@arm.com return NoFault; 22910259SAndrew.Bardsley@arm.com#endif 23010259SAndrew.Bardsley@arm.com } 23110259SAndrew.Bardsley@arm.com 23210259SAndrew.Bardsley@arm.com bool 23310259SAndrew.Bardsley@arm.com simPalCheck(int palFunc) 23410259SAndrew.Bardsley@arm.com { 23510259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 23610259SAndrew.Bardsley@arm.com return thread.simPalCheck(palFunc); 23710259SAndrew.Bardsley@arm.com#else 23810259SAndrew.Bardsley@arm.com return false; 23910259SAndrew.Bardsley@arm.com#endif 24010259SAndrew.Bardsley@arm.com } 24110259SAndrew.Bardsley@arm.com 24210259SAndrew.Bardsley@arm.com void 24310259SAndrew.Bardsley@arm.com syscall(int64_t callnum) 24410259SAndrew.Bardsley@arm.com { 24510259SAndrew.Bardsley@arm.com if (FullSystem) 24610259SAndrew.Bardsley@arm.com panic("Syscall emulation isn't available in FS mode.\n"); 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.com thread.syscall(callnum); 24910259SAndrew.Bardsley@arm.com } 25010259SAndrew.Bardsley@arm.com 25110259SAndrew.Bardsley@arm.com ThreadContext *tcBase() { return thread.getTC(); } 25210259SAndrew.Bardsley@arm.com 25310259SAndrew.Bardsley@arm.com /* @todo, should make stCondFailures persistent somewhere */ 25410319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const { return 0; } 25510319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int st_cond_failures) {} 25610259SAndrew.Bardsley@arm.com 25710259SAndrew.Bardsley@arm.com int contextId() { return thread.contextId(); } 25810259SAndrew.Bardsley@arm.com /* ISA-specific (or at least currently ISA singleton) functions */ 25910259SAndrew.Bardsley@arm.com 26010259SAndrew.Bardsley@arm.com /* X86: TLB twiddling */ 26110259SAndrew.Bardsley@arm.com void 26210259SAndrew.Bardsley@arm.com demapPage(Addr vaddr, uint64_t asn) 26310259SAndrew.Bardsley@arm.com { 26410259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 26510259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 26610259SAndrew.Bardsley@arm.com } 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.com TheISA::CCReg 26910259SAndrew.Bardsley@arm.com readCCRegOperand(const StaticInst *si, int idx) 27010259SAndrew.Bardsley@arm.com { 27110259SAndrew.Bardsley@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 27210259SAndrew.Bardsley@arm.com return thread.readCCReg(reg_idx); 27310259SAndrew.Bardsley@arm.com } 27410259SAndrew.Bardsley@arm.com 27510259SAndrew.Bardsley@arm.com void 27610259SAndrew.Bardsley@arm.com setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) 27710259SAndrew.Bardsley@arm.com { 27810259SAndrew.Bardsley@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 27910259SAndrew.Bardsley@arm.com thread.setCCReg(reg_idx, val); 28010259SAndrew.Bardsley@arm.com } 28110259SAndrew.Bardsley@arm.com 28210259SAndrew.Bardsley@arm.com void 28310259SAndrew.Bardsley@arm.com demapInstPage(Addr vaddr, uint64_t asn) 28410259SAndrew.Bardsley@arm.com { 28510259SAndrew.Bardsley@arm.com thread.getITBPtr()->demapPage(vaddr, asn); 28610259SAndrew.Bardsley@arm.com } 28710259SAndrew.Bardsley@arm.com 28810259SAndrew.Bardsley@arm.com void 28910259SAndrew.Bardsley@arm.com demapDataPage(Addr vaddr, uint64_t asn) 29010259SAndrew.Bardsley@arm.com { 29110259SAndrew.Bardsley@arm.com thread.getDTBPtr()->demapPage(vaddr, asn); 29210259SAndrew.Bardsley@arm.com } 29310259SAndrew.Bardsley@arm.com 29410259SAndrew.Bardsley@arm.com /* ALPHA/POWER: Effective address storage */ 29510319SAndreas.Sandberg@ARM.com void setEA(Addr ea) 29610259SAndrew.Bardsley@arm.com { 29710259SAndrew.Bardsley@arm.com inst->ea = ea; 29810259SAndrew.Bardsley@arm.com } 29910259SAndrew.Bardsley@arm.com 30010259SAndrew.Bardsley@arm.com BaseCPU *getCpuPtr() { return &cpu; } 30110259SAndrew.Bardsley@arm.com 30210259SAndrew.Bardsley@arm.com /* POWER: Effective address storage */ 30310319SAndreas.Sandberg@ARM.com Addr getEA() const 30410259SAndrew.Bardsley@arm.com { 30510259SAndrew.Bardsley@arm.com return inst->ea; 30610259SAndrew.Bardsley@arm.com } 30710259SAndrew.Bardsley@arm.com 30810259SAndrew.Bardsley@arm.com /* MIPS: other thread register reading/writing */ 30910259SAndrew.Bardsley@arm.com uint64_t 31010319SAndreas.Sandberg@ARM.com readRegOtherThread(int idx, ThreadID tid = InvalidThreadID) 31110259SAndrew.Bardsley@arm.com { 31210259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 31310259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 31410259SAndrew.Bardsley@arm.com 31510259SAndrew.Bardsley@arm.com if (idx < TheISA::FP_Reg_Base) { /* Integer */ 31610259SAndrew.Bardsley@arm.com return other_thread->readIntReg(idx); 31710259SAndrew.Bardsley@arm.com } else if (idx < TheISA::Misc_Reg_Base) { /* Float */ 31810259SAndrew.Bardsley@arm.com return other_thread->readFloatRegBits(idx 31910259SAndrew.Bardsley@arm.com - TheISA::FP_Reg_Base); 32010259SAndrew.Bardsley@arm.com } else { /* Misc */ 32110259SAndrew.Bardsley@arm.com return other_thread->readMiscReg(idx 32210259SAndrew.Bardsley@arm.com - TheISA::Misc_Reg_Base); 32310259SAndrew.Bardsley@arm.com } 32410259SAndrew.Bardsley@arm.com } 32510259SAndrew.Bardsley@arm.com 32610259SAndrew.Bardsley@arm.com void 32710319SAndreas.Sandberg@ARM.com setRegOtherThread(int idx, const TheISA::MiscReg &val, 32810259SAndrew.Bardsley@arm.com ThreadID tid = InvalidThreadID) 32910259SAndrew.Bardsley@arm.com { 33010259SAndrew.Bardsley@arm.com SimpleThread *other_thread = (tid == InvalidThreadID 33110259SAndrew.Bardsley@arm.com ? &thread : cpu.threads[tid]); 33210259SAndrew.Bardsley@arm.com 33310259SAndrew.Bardsley@arm.com if (idx < TheISA::FP_Reg_Base) { /* Integer */ 33410259SAndrew.Bardsley@arm.com return other_thread->setIntReg(idx, val); 33510259SAndrew.Bardsley@arm.com } else if (idx < TheISA::Misc_Reg_Base) { /* Float */ 33610259SAndrew.Bardsley@arm.com return other_thread->setFloatRegBits(idx 33710259SAndrew.Bardsley@arm.com - TheISA::FP_Reg_Base, val); 33810259SAndrew.Bardsley@arm.com } else { /* Misc */ 33910259SAndrew.Bardsley@arm.com return other_thread->setMiscReg(idx 34010259SAndrew.Bardsley@arm.com - TheISA::Misc_Reg_Base, val); 34110259SAndrew.Bardsley@arm.com } 34210259SAndrew.Bardsley@arm.com } 34310529Smorr@cs.wisc.edu 34410529Smorr@cs.wisc.edu public: 34510529Smorr@cs.wisc.edu // monitor/mwait funtions 34610529Smorr@cs.wisc.edu void armMonitor(Addr address) { getCpuPtr()->armMonitor(address); } 34710529Smorr@cs.wisc.edu bool mwait(PacketPtr pkt) { return getCpuPtr()->mwait(pkt); } 34810529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 34910529Smorr@cs.wisc.edu { return getCpuPtr()->mwaitAtomic(tc, thread.dtb); } 35010529Smorr@cs.wisc.edu AddressMonitor *getAddrMonitor() 35110529Smorr@cs.wisc.edu { return getCpuPtr()->getCpuAddrMonitor(); } 35210259SAndrew.Bardsley@arm.com}; 35310259SAndrew.Bardsley@arm.com 35410259SAndrew.Bardsley@arm.com} 35510259SAndrew.Bardsley@arm.com 35610259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 357