decode.cc revision 11321:02e930db812d
12632Sstever@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2013-2014 ARM Limited 32632Sstever@eecs.umich.edu * All rights reserved 42632Sstever@eecs.umich.edu * 52632Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 62632Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 72632Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 82632Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 94479Sbinkertn@umich.edu * licensed hereunder. You may use the software subject to the license 104479Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated 114479Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software, 122632Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 132632Sstever@eecs.umich.edu * 142632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 152632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 162632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 172632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 182632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 192632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 202632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 212632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 222632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 232632Sstever@eecs.umich.edu * this software without specific prior written permission. 242632Sstever@eecs.umich.edu * 252632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282632Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292632Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302632Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312632Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362632Sstever@eecs.umich.edu * 372632Sstever@eecs.umich.edu * Authors: Andrew Bardsley 382632Sstever@eecs.umich.edu */ 392632Sstever@eecs.umich.edu 402632Sstever@eecs.umich.edu#include "cpu/minor/decode.hh" 412632Sstever@eecs.umich.edu#include "cpu/minor/pipeline.hh" 422632Sstever@eecs.umich.edu#include "debug/Decode.hh" 432632Sstever@eecs.umich.edu 442632Sstever@eecs.umich.edunamespace Minor 452632Sstever@eecs.umich.edu{ 462632Sstever@eecs.umich.edu 472632Sstever@eecs.umich.eduDecode::Decode(const std::string &name, 482632Sstever@eecs.umich.edu MinorCPU &cpu_, 492632Sstever@eecs.umich.edu MinorCPUParams ¶ms, 502632Sstever@eecs.umich.edu Latch<ForwardInstData>::Output inp_, 512632Sstever@eecs.umich.edu Latch<ForwardInstData>::Input out_, 522632Sstever@eecs.umich.edu Reservable &next_stage_input_buffer) : 532632Sstever@eecs.umich.edu Named(name), 542632Sstever@eecs.umich.edu cpu(cpu_), 552632Sstever@eecs.umich.edu inp(inp_), 562632Sstever@eecs.umich.edu out(out_), 572632Sstever@eecs.umich.edu nextStageReserve(next_stage_input_buffer), 58 outputWidth(params.executeInputWidth), 59 processMoreThanOneInput(params.decodeCycleInput), 60 inputBuffer(name + ".inputBuffer", "insts", params.decodeInputBufferSize), 61 inputIndex(0), 62 inMacroop(false), 63 execSeqNum(InstId::firstExecSeqNum), 64 blocked(false) 65{ 66 if (outputWidth < 1) 67 fatal("%s: executeInputWidth must be >= 1 (%d)\n", name, outputWidth); 68 69 if (params.decodeInputBufferSize < 1) { 70 fatal("%s: decodeInputBufferSize must be >= 1 (%d)\n", name, 71 params.decodeInputBufferSize); 72 } 73} 74 75const ForwardInstData * 76Decode::getInput() 77{ 78 /* Get insts from the inputBuffer to work with */ 79 if (!inputBuffer.empty()) { 80 const ForwardInstData &head = inputBuffer.front(); 81 82 return (head.isBubble() ? NULL : &(inputBuffer.front())); 83 } else { 84 return NULL; 85 } 86} 87 88void 89Decode::popInput() 90{ 91 if (!inputBuffer.empty()) 92 inputBuffer.pop(); 93 94 inputIndex = 0; 95 inMacroop = false; 96} 97 98#if TRACING_ON 99/** Add the tracing data to an instruction. This originates in 100 * decode because this is the first place that execSeqNums are known 101 * (these are used as the 'FetchSeq' in tracing data) */ 102static void 103dynInstAddTracing(MinorDynInstPtr inst, StaticInstPtr static_inst, 104 MinorCPU &cpu) 105{ 106 inst->traceData = cpu.getTracer()->getInstRecord(curTick(), 107 cpu.getContext(inst->id.threadId), 108 inst->staticInst, inst->pc, static_inst); 109 110 /* Use the execSeqNum as the fetch sequence number as this most closely 111 * matches the other processor models' idea of fetch sequence */ 112 if (inst->traceData) 113 inst->traceData->setFetchSeq(inst->id.execSeqNum); 114} 115#endif 116 117void 118Decode::evaluate() 119{ 120 inputBuffer.setTail(*inp.outputWire); 121 ForwardInstData &insts_out = *out.inputWire; 122 123 assert(insts_out.isBubble()); 124 125 blocked = false; 126 127 if (!nextStageReserve.canReserve()) { 128 blocked = true; 129 } else { 130 const ForwardInstData *insts_in = getInput(); 131 132 unsigned int output_index = 0; 133 134 /* Pack instructions into the output while we can. This may involve 135 * using more than one input line */ 136 while (insts_in && 137 inputIndex < insts_in->width() && /* Still more input */ 138 output_index < outputWidth /* Still more output to fill */) 139 { 140 MinorDynInstPtr inst = insts_in->insts[inputIndex]; 141 142 if (inst->isBubble()) { 143 /* Skip */ 144 inputIndex++; 145 inMacroop = false; 146 } else { 147 StaticInstPtr static_inst = inst->staticInst; 148 /* Static inst of a macro-op above the output_inst */ 149 StaticInstPtr parent_static_inst = NULL; 150 MinorDynInstPtr output_inst = inst; 151 152 if (inst->isFault()) { 153 DPRINTF(Decode, "Fault being passed: %d\n", 154 inst->fault->name()); 155 156 inputIndex++; 157 inMacroop = false; 158 } else if (static_inst->isMacroop()) { 159 /* Generate a new micro-op */ 160 StaticInstPtr static_micro_inst; 161 162 /* Set up PC for the next micro-op emitted */ 163 if (!inMacroop) { 164 microopPC = inst->pc; 165 inMacroop = true; 166 } 167 168 /* Get the micro-op static instruction from the 169 * static_inst. */ 170 static_micro_inst = 171 static_inst->fetchMicroop(microopPC.microPC()); 172 173 output_inst = new MinorDynInst(inst->id); 174 output_inst->pc = microopPC; 175 output_inst->staticInst = static_micro_inst; 176 output_inst->fault = NoFault; 177 178 /* Allow a predicted next address only on the last 179 * microop */ 180 if (static_micro_inst->isLastMicroop()) { 181 output_inst->predictedTaken = inst->predictedTaken; 182 output_inst->predictedTarget = inst->predictedTarget; 183 } 184 185 DPRINTF(Decode, "Microop decomposition inputIndex:" 186 " %d output_index: %d lastMicroop: %s microopPC:" 187 " %d.%d inst: %d\n", 188 inputIndex, output_index, 189 (static_micro_inst->isLastMicroop() ? 190 "true" : "false"), 191 microopPC.instAddr(), microopPC.microPC(), 192 *output_inst); 193 194 /* Acknowledge that the static_inst isn't mine, it's my 195 * parent macro-op's */ 196 parent_static_inst = static_inst; 197 198 static_micro_inst->advancePC(microopPC); 199 200 /* Step input if this is the last micro-op */ 201 if (static_micro_inst->isLastMicroop()) { 202 inputIndex++; 203 inMacroop = false; 204 } 205 } else { 206 /* Doesn't need decomposing, pass on instruction */ 207 DPRINTF(Decode, "Passing on inst: %s inputIndex:" 208 " %d output_index: %d\n", 209 *output_inst, inputIndex, output_index); 210 211 parent_static_inst = static_inst; 212 213 /* Step input */ 214 inputIndex++; 215 inMacroop = false; 216 } 217 218 /* Set execSeqNum of output_inst */ 219 output_inst->id.execSeqNum = execSeqNum; 220 /* Add tracing */ 221#if TRACING_ON 222 dynInstAddTracing(output_inst, parent_static_inst, cpu); 223#endif 224 225 /* Step to next sequence number */ 226 execSeqNum++; 227 228 /* Correctly size the output before writing */ 229 if (output_index == 0) insts_out.resize(outputWidth); 230 /* Push into output */ 231 insts_out.insts[output_index] = output_inst; 232 output_index++; 233 } 234 235 /* Have we finished with the input? */ 236 if (inputIndex == insts_in->width()) { 237 /* If we have just been producing micro-ops, we *must* have 238 * got to the end of that for inputIndex to be pushed past 239 * insts_in->width() */ 240 assert(!inMacroop); 241 popInput(); 242 insts_in = NULL; 243 244 if (processMoreThanOneInput) { 245 DPRINTF(Decode, "Wrapping\n"); 246 insts_in = getInput(); 247 } 248 } 249 } 250 251 /* The rest of the output (if any) should already have been packed 252 * with bubble instructions by insts_out's initialisation 253 * 254 * for (; output_index < outputWidth; output_index++) 255 * assert(insts_out.insts[output_index]->isBubble()); 256 */ 257 } 258 259 /* If we generated output, reserve space for the result in the next stage 260 * and mark the stage as being active this cycle */ 261 if (!insts_out.isBubble()) { 262 /* Note activity of following buffer */ 263 cpu.activityRecorder->activity(); 264 nextStageReserve.reserve(); 265 } 266 267 /* If we still have input to process and somewhere to put it, 268 * mark stage as active */ 269 if (getInput() && nextStageReserve.canReserve()) 270 cpu.activityRecorder->activateStage(Pipeline::DecodeStageId); 271 272 /* Make sure the input (if any left) is pushed */ 273 inputBuffer.pushTail(); 274} 275 276bool 277Decode::isDrained() 278{ 279 return inputBuffer.empty() && (*inp.outputWire).isBubble(); 280} 281 282void 283Decode::minorTrace() const 284{ 285 std::ostringstream data; 286 287 if (blocked) 288 data << 'B'; 289 else 290 (*out.inputWire).reportData(data); 291 292 MINORTRACE("insts=%s\n", data.str()); 293 inputBuffer.minorTrace(); 294} 295 296} 297