cpu.hh revision 11567
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2012-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com/** 4110259SAndrew.Bardsley@arm.com * @file 4210259SAndrew.Bardsley@arm.com * 4310259SAndrew.Bardsley@arm.com * Top level definition of the Minor in-order CPU model 4410259SAndrew.Bardsley@arm.com */ 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_CPU_HH__ 4710259SAndrew.Bardsley@arm.com#define __CPU_MINOR_CPU_HH__ 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/activity.hh" 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/stats.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 5311567Smitch.hayenga@arm.com#include "enums/ThreadPolicy.hh" 5410259SAndrew.Bardsley@arm.com#include "params/MinorCPU.hh" 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.comnamespace Minor 5710259SAndrew.Bardsley@arm.com{ 5810259SAndrew.Bardsley@arm.com/** Forward declared to break the cyclic inclusion dependencies between 5910259SAndrew.Bardsley@arm.com * pipeline and cpu */ 6010259SAndrew.Bardsley@arm.comclass Pipeline; 6110259SAndrew.Bardsley@arm.com 6210259SAndrew.Bardsley@arm.com/** Minor will use the SimpleThread state for now */ 6310259SAndrew.Bardsley@arm.comtypedef SimpleThread MinorThread; 6410259SAndrew.Bardsley@arm.com}; 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com/** 6710259SAndrew.Bardsley@arm.com * MinorCPU is an in-order CPU model with four fixed pipeline stages: 6810259SAndrew.Bardsley@arm.com * 6910259SAndrew.Bardsley@arm.com * Fetch1 - fetches lines from memory 7010259SAndrew.Bardsley@arm.com * Fetch2 - decomposes lines into macro-op instructions 7110259SAndrew.Bardsley@arm.com * Decode - decomposes macro-ops into micro-ops 7210259SAndrew.Bardsley@arm.com * Execute - executes those micro-ops 7310259SAndrew.Bardsley@arm.com * 7410259SAndrew.Bardsley@arm.com * This pipeline is carried in the MinorCPU::pipeline object. 7510259SAndrew.Bardsley@arm.com * The exec_context interface is not carried by MinorCPU but by 7610259SAndrew.Bardsley@arm.com * Minor::ExecContext objects 7710259SAndrew.Bardsley@arm.com * created by Minor::Execute. 7810259SAndrew.Bardsley@arm.com */ 7910259SAndrew.Bardsley@arm.comclass MinorCPU : public BaseCPU 8010259SAndrew.Bardsley@arm.com{ 8110259SAndrew.Bardsley@arm.com protected: 8210259SAndrew.Bardsley@arm.com /** pipeline is a container for the clockable pipeline stage objects. 8310259SAndrew.Bardsley@arm.com * Elements of pipeline call TheISA to implement the model. */ 8410259SAndrew.Bardsley@arm.com Minor::Pipeline *pipeline; 8510259SAndrew.Bardsley@arm.com 8610259SAndrew.Bardsley@arm.com public: 8710259SAndrew.Bardsley@arm.com /** Activity recording for pipeline. This belongs to Pipeline but 8810259SAndrew.Bardsley@arm.com * stages will access it through the CPU as the MinorCPU object 8910259SAndrew.Bardsley@arm.com * actually mediates idling behaviour */ 9010259SAndrew.Bardsley@arm.com Minor::MinorActivityRecorder *activityRecorder; 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.com /** These are thread state-representing objects for this CPU. If 9310259SAndrew.Bardsley@arm.com * you need a ThreadContext for *any* reason, use 9410259SAndrew.Bardsley@arm.com * threads[threadId]->getTC() */ 9510259SAndrew.Bardsley@arm.com std::vector<Minor::MinorThread *> threads; 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.com public: 9810259SAndrew.Bardsley@arm.com /** Provide a non-protected base class for Minor's Ports as derived 9910259SAndrew.Bardsley@arm.com * classes are created by Fetch1 and Execute */ 10010259SAndrew.Bardsley@arm.com class MinorCPUPort : public MasterPort 10110259SAndrew.Bardsley@arm.com { 10210259SAndrew.Bardsley@arm.com public: 10310259SAndrew.Bardsley@arm.com /** The enclosing cpu */ 10410259SAndrew.Bardsley@arm.com MinorCPU &cpu; 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com public: 10710259SAndrew.Bardsley@arm.com MinorCPUPort(const std::string& name_, MinorCPU &cpu_) 10810259SAndrew.Bardsley@arm.com : MasterPort(name_, &cpu_), cpu(cpu_) 10910259SAndrew.Bardsley@arm.com { } 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.com }; 11210259SAndrew.Bardsley@arm.com 11311567Smitch.hayenga@arm.com /** Thread Scheduling Policy (RoundRobin, Random, etc) */ 11411567Smitch.hayenga@arm.com Enums::ThreadPolicy threadPolicy; 11510259SAndrew.Bardsley@arm.com protected: 11610259SAndrew.Bardsley@arm.com /** Return a reference to the data port. */ 11711169Sandreas.hansson@arm.com MasterPort &getDataPort() override; 11810259SAndrew.Bardsley@arm.com 11910259SAndrew.Bardsley@arm.com /** Return a reference to the instruction port. */ 12011169Sandreas.hansson@arm.com MasterPort &getInstPort() override; 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com public: 12310259SAndrew.Bardsley@arm.com MinorCPU(MinorCPUParams *params); 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.com ~MinorCPU(); 12610259SAndrew.Bardsley@arm.com 12710259SAndrew.Bardsley@arm.com public: 12810259SAndrew.Bardsley@arm.com /** Starting, waking and initialisation */ 12911169Sandreas.hansson@arm.com void init() override; 13011169Sandreas.hansson@arm.com void startup() override; 13111168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override; 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com Addr dbg_vtophys(Addr addr); 13410259SAndrew.Bardsley@arm.com 13510259SAndrew.Bardsley@arm.com /** Processor-specific statistics */ 13610259SAndrew.Bardsley@arm.com Minor::MinorStats stats; 13710259SAndrew.Bardsley@arm.com 13810259SAndrew.Bardsley@arm.com /** Stats interface from SimObject (by way of BaseCPU) */ 13911169Sandreas.hansson@arm.com void regStats() override; 14010259SAndrew.Bardsley@arm.com 14110259SAndrew.Bardsley@arm.com /** Simple inst count interface from BaseCPU */ 14211169Sandreas.hansson@arm.com Counter totalInsts() const override; 14311169Sandreas.hansson@arm.com Counter totalOps() const override; 14410259SAndrew.Bardsley@arm.com 14511168Sandreas.hansson@arm.com void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 14611168Sandreas.hansson@arm.com void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 14710259SAndrew.Bardsley@arm.com 14810259SAndrew.Bardsley@arm.com /** Serialize pipeline data */ 14911169Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15011169Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 15110259SAndrew.Bardsley@arm.com 15210259SAndrew.Bardsley@arm.com /** Drain interface */ 15311168Sandreas.hansson@arm.com DrainState drain() override; 15411168Sandreas.hansson@arm.com void drainResume() override; 15510913Sandreas.sandberg@arm.com /** Signal from Pipeline that MinorCPU should signal that a drain 15610913Sandreas.sandberg@arm.com * is complete and set its drainState */ 15710259SAndrew.Bardsley@arm.com void signalDrainDone(); 15811169Sandreas.hansson@arm.com void memWriteback() override; 15910259SAndrew.Bardsley@arm.com 16010259SAndrew.Bardsley@arm.com /** Switching interface from BaseCPU */ 16111169Sandreas.hansson@arm.com void switchOut() override; 16211169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *old_cpu) override; 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com /** Thread activation interface from BaseCPU. */ 16511169Sandreas.hansson@arm.com void activateContext(ThreadID thread_id) override; 16611169Sandreas.hansson@arm.com void suspendContext(ThreadID thread_id) override; 16710259SAndrew.Bardsley@arm.com 16811567Smitch.hayenga@arm.com /** Thread scheduling utility functions */ 16911567Smitch.hayenga@arm.com std::vector<ThreadID> roundRobinPriority(ThreadID priority) 17011567Smitch.hayenga@arm.com { 17111567Smitch.hayenga@arm.com std::vector<ThreadID> prio_list; 17211567Smitch.hayenga@arm.com for (ThreadID i = 1; i <= numThreads; i++) { 17311567Smitch.hayenga@arm.com prio_list.push_back((priority + i) % numThreads); 17411567Smitch.hayenga@arm.com } 17511567Smitch.hayenga@arm.com return prio_list; 17611567Smitch.hayenga@arm.com } 17711567Smitch.hayenga@arm.com 17811567Smitch.hayenga@arm.com std::vector<ThreadID> randomPriority() 17911567Smitch.hayenga@arm.com { 18011567Smitch.hayenga@arm.com std::vector<ThreadID> prio_list; 18111567Smitch.hayenga@arm.com for (ThreadID i = 0; i < numThreads; i++) { 18211567Smitch.hayenga@arm.com prio_list.push_back(i); 18311567Smitch.hayenga@arm.com } 18411567Smitch.hayenga@arm.com std::random_shuffle(prio_list.begin(), prio_list.end()); 18511567Smitch.hayenga@arm.com return prio_list; 18611567Smitch.hayenga@arm.com } 18711567Smitch.hayenga@arm.com 18810259SAndrew.Bardsley@arm.com /** Interface for stages to signal that they have become active after 18910259SAndrew.Bardsley@arm.com * a callback or eventq event where the pipeline itself may have 19010259SAndrew.Bardsley@arm.com * already been idled. The stage argument should be from the 19110259SAndrew.Bardsley@arm.com * enumeration Pipeline::StageId */ 19210259SAndrew.Bardsley@arm.com void wakeupOnEvent(unsigned int stage_id); 19310259SAndrew.Bardsley@arm.com}; 19410259SAndrew.Bardsley@arm.com 19510259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_CPU_HH__ */ 196