cpu.hh revision 10905
17138Sgblack@eecs.umich.edu/*
27138Sgblack@eecs.umich.edu * Copyright (c) 2012-2014 ARM Limited
310037SARM gem5 Developers * All rights reserved
47138Sgblack@eecs.umich.edu *
57138Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall
67138Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual
77138Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating
87138Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software
97138Sgblack@eecs.umich.edu * licensed hereunder.  You may use the software subject to the license
107138Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated
117138Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software,
127138Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form.
137138Sgblack@eecs.umich.edu *
147138Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
157138Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
167138Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
177138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
187138Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
197138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
207138Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
217138Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
227138Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
237138Sgblack@eecs.umich.edu * this software without specific prior written permission.
247138Sgblack@eecs.umich.edu *
257138Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
267138Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
277138Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
287138Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
297138Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
307138Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
317138Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
327138Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
337138Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
347138Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
357138Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
367138Sgblack@eecs.umich.edu *
377138Sgblack@eecs.umich.edu * Authors: Andrew Bardsley
387138Sgblack@eecs.umich.edu */
397138Sgblack@eecs.umich.edu
407138Sgblack@eecs.umich.edu/**
417138Sgblack@eecs.umich.edu * @file
427138Sgblack@eecs.umich.edu *
437138Sgblack@eecs.umich.edu *  Top level definition of the Minor in-order CPU model
447138Sgblack@eecs.umich.edu */
457138Sgblack@eecs.umich.edu
467214Sgblack@eecs.umich.edu#ifndef __CPU_MINOR_CPU_HH__
478303SAli.Saidi@ARM.com#define __CPU_MINOR_CPU_HH__
487214Sgblack@eecs.umich.edu
497214Sgblack@eecs.umich.edu#include "cpu/minor/activity.hh"
507138Sgblack@eecs.umich.edu#include "cpu/minor/stats.hh"
518302SAli.Saidi@ARM.com#include "cpu/base.hh"
527138Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh"
537138Sgblack@eecs.umich.edu#include "params/MinorCPU.hh"
548305SAli.Saidi@ARM.com
558305SAli.Saidi@ARM.comnamespace Minor
568305SAli.Saidi@ARM.com{
578305SAli.Saidi@ARM.com/** Forward declared to break the cyclic inclusion dependencies between
588305SAli.Saidi@ARM.com *  pipeline and cpu */
598305SAli.Saidi@ARM.comclass Pipeline;
608305SAli.Saidi@ARM.com
618305SAli.Saidi@ARM.com/** Minor will use the SimpleThread state for now */
628305SAli.Saidi@ARM.comtypedef SimpleThread MinorThread;
638305SAli.Saidi@ARM.com};
648305SAli.Saidi@ARM.com
658305SAli.Saidi@ARM.com/**
668305SAli.Saidi@ARM.com *  MinorCPU is an in-order CPU model with four fixed pipeline stages:
678305SAli.Saidi@ARM.com *
688305SAli.Saidi@ARM.com *  Fetch1 - fetches lines from memory
698305SAli.Saidi@ARM.com *  Fetch2 - decomposes lines into macro-op instructions
708305SAli.Saidi@ARM.com *  Decode - decomposes macro-ops into micro-ops
718305SAli.Saidi@ARM.com *  Execute - executes those micro-ops
728305SAli.Saidi@ARM.com *
738305SAli.Saidi@ARM.com *  This pipeline is carried in the MinorCPU::pipeline object.
748305SAli.Saidi@ARM.com *  The exec_context interface is not carried by MinorCPU but by
758305SAli.Saidi@ARM.com *      Minor::ExecContext objects
768305SAli.Saidi@ARM.com *  created by Minor::Execute.
778305SAli.Saidi@ARM.com */
787138Sgblack@eecs.umich.educlass MinorCPU : public BaseCPU
797138Sgblack@eecs.umich.edu{
808303SAli.Saidi@ARM.com  protected:
817138Sgblack@eecs.umich.edu    /** pipeline is a container for the clockable pipeline stage objects.
828305SAli.Saidi@ARM.com     *  Elements of pipeline call TheISA to implement the model. */
838305SAli.Saidi@ARM.com    Minor::Pipeline *pipeline;
847193Sgblack@eecs.umich.edu
857138Sgblack@eecs.umich.edu  public:
867215Sgblack@eecs.umich.edu    /** Activity recording for pipeline.  This belongs to Pipeline but
877138Sgblack@eecs.umich.edu     *  stages will access it through the CPU as the MinorCPU object
887138Sgblack@eecs.umich.edu     *  actually mediates idling behaviour */
897138Sgblack@eecs.umich.edu    Minor::MinorActivityRecorder *activityRecorder;
907138Sgblack@eecs.umich.edu
917138Sgblack@eecs.umich.edu    /** These are thread state-representing objects for this CPU.  If
927138Sgblack@eecs.umich.edu     *  you need a ThreadContext for *any* reason, use
937138Sgblack@eecs.umich.edu     *  threads[threadId]->getTC() */
947138Sgblack@eecs.umich.edu    std::vector<Minor::MinorThread *> threads;
957138Sgblack@eecs.umich.edu
967138Sgblack@eecs.umich.edu  public:
977138Sgblack@eecs.umich.edu    /** Provide a non-protected base class for Minor's Ports as derived
987138Sgblack@eecs.umich.edu     *  classes are created by Fetch1 and Execute */
997138Sgblack@eecs.umich.edu    class MinorCPUPort : public MasterPort
1007138Sgblack@eecs.umich.edu    {
1017138Sgblack@eecs.umich.edu      public:
1028305SAli.Saidi@ARM.com        /** The enclosing cpu */
1038305SAli.Saidi@ARM.com        MinorCPU &cpu;
1047193Sgblack@eecs.umich.edu
1057138Sgblack@eecs.umich.edu      public:
1067215Sgblack@eecs.umich.edu        MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
1077138Sgblack@eecs.umich.edu            : MasterPort(name_, &cpu_), cpu(cpu_)
1087138Sgblack@eecs.umich.edu        { }
1097138Sgblack@eecs.umich.edu
1108305SAli.Saidi@ARM.com      protected:
1117138Sgblack@eecs.umich.edu        /** Snooping a coherence request, do nothing.  */
1127138Sgblack@eecs.umich.edu        virtual void recvTimingSnoopReq(PacketPtr pkt) { }
1137138Sgblack@eecs.umich.edu    };
1147138Sgblack@eecs.umich.edu
1158304SAli.Saidi@ARM.com    /** The DrainManager passed into drain that needs be signalled when
1168304SAli.Saidi@ARM.com     *  draining is complete */
1177138Sgblack@eecs.umich.edu    DrainManager *drainManager;
1187193Sgblack@eecs.umich.edu
1199250SAli.Saidi@ARM.com  protected:
1209250SAli.Saidi@ARM.com     /** Return a reference to the data port. */
1217138Sgblack@eecs.umich.edu    MasterPort &getDataPort();
1227138Sgblack@eecs.umich.edu
1237138Sgblack@eecs.umich.edu    /** Return a reference to the instruction port. */
1247138Sgblack@eecs.umich.edu    MasterPort &getInstPort();
1257138Sgblack@eecs.umich.edu
1267193Sgblack@eecs.umich.edu  public:
1277184Sgblack@eecs.umich.edu    MinorCPU(MinorCPUParams *params);
1287214Sgblack@eecs.umich.edu
1297214Sgblack@eecs.umich.edu    ~MinorCPU();
1307138Sgblack@eecs.umich.edu
1318305SAli.Saidi@ARM.com  public:
1328305SAli.Saidi@ARM.com    /** Starting, waking and initialisation */
1338305SAli.Saidi@ARM.com    void init();
1347184Sgblack@eecs.umich.edu    void startup();
1357188Sgblack@eecs.umich.edu    void wakeup();
1368304SAli.Saidi@ARM.com
1379250SAli.Saidi@ARM.com    Addr dbg_vtophys(Addr addr);
1388304SAli.Saidi@ARM.com
1397188Sgblack@eecs.umich.edu    /** Processor-specific statistics */
1408304SAli.Saidi@ARM.com    Minor::MinorStats stats;
1418304SAli.Saidi@ARM.com
1429250SAli.Saidi@ARM.com    /** Stats interface from SimObject (by way of BaseCPU) */
1438304SAli.Saidi@ARM.com    void regStats();
1447184Sgblack@eecs.umich.edu
1457188Sgblack@eecs.umich.edu    /** Simple inst count interface from BaseCPU */
1467188Sgblack@eecs.umich.edu    Counter totalInsts() const;
1477188Sgblack@eecs.umich.edu    Counter totalOps() const;
1487188Sgblack@eecs.umich.edu
1497188Sgblack@eecs.umich.edu    void serializeThread(CheckpointOut &cp,
1507188Sgblack@eecs.umich.edu                         ThreadID tid) const M5_ATTR_OVERRIDE;
1517193Sgblack@eecs.umich.edu    void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
1527193Sgblack@eecs.umich.edu
1537188Sgblack@eecs.umich.edu    /** Serialize pipeline data */
1547188Sgblack@eecs.umich.edu    void serialize(CheckpointOut &cp) const;
1557188Sgblack@eecs.umich.edu    void unserialize(CheckpointIn &cp);
1567193Sgblack@eecs.umich.edu
1578203SAli.Saidi@ARM.com    /** Drain interface */
1588203SAli.Saidi@ARM.com    unsigned int drain(DrainManager *drain_manager);
1597184Sgblack@eecs.umich.edu    void drainResume();
1607184Sgblack@eecs.umich.edu    /** Signal from Pipeline that MinorCPU should signal the DrainManager
1617184Sgblack@eecs.umich.edu     *  that a drain is complete and set its drainState */
1628305SAli.Saidi@ARM.com    void signalDrainDone();
1637184Sgblack@eecs.umich.edu    void memWriteback();
1647184Sgblack@eecs.umich.edu
1657193Sgblack@eecs.umich.edu    /** Switching interface from BaseCPU */
1667184Sgblack@eecs.umich.edu    void switchOut();
1677214Sgblack@eecs.umich.edu    void takeOverFrom(BaseCPU *old_cpu);
1687215Sgblack@eecs.umich.edu
1697184Sgblack@eecs.umich.edu    /** Thread activation interface from BaseCPU. */
1708305SAli.Saidi@ARM.com    void activateContext(ThreadID thread_id);
1718305SAli.Saidi@ARM.com    void suspendContext(ThreadID thread_id);
1728305SAli.Saidi@ARM.com
1737184Sgblack@eecs.umich.edu    /** Interface for stages to signal that they have become active after
1748305SAli.Saidi@ARM.com     *  a callback or eventq event where the pipeline itself may have
1758305SAli.Saidi@ARM.com     *  already been idled.  The stage argument should be from the
1768305SAli.Saidi@ARM.com     *  enumeration Pipeline::StageId */
1778305SAli.Saidi@ARM.com    void wakeupOnEvent(unsigned int stage_id);
1788305SAli.Saidi@ARM.com};
1798305SAli.Saidi@ARM.com
1807188Sgblack@eecs.umich.edu#endif /* __CPU_MINOR_CPU_HH__ */
1818304SAli.Saidi@ARM.com