cpu.cc revision 11567
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2012-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com#include "arch/utility.hh" 4110259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 4210259SAndrew.Bardsley@arm.com#include "cpu/minor/dyn_inst.hh" 4310259SAndrew.Bardsley@arm.com#include "cpu/minor/fetch1.hh" 4410259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 4510259SAndrew.Bardsley@arm.com#include "debug/Drain.hh" 4610259SAndrew.Bardsley@arm.com#include "debug/MinorCPU.hh" 4710259SAndrew.Bardsley@arm.com#include "debug/Quiesce.hh" 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.comMinorCPU::MinorCPU(MinorCPUParams *params) : 5011567Smitch.hayenga@arm.com BaseCPU(params), 5111567Smitch.hayenga@arm.com threadPolicy(params->threadPolicy) 5210259SAndrew.Bardsley@arm.com{ 5310259SAndrew.Bardsley@arm.com /* This is only written for one thread at the moment */ 5410259SAndrew.Bardsley@arm.com Minor::MinorThread *thread; 5510259SAndrew.Bardsley@arm.com 5611567Smitch.hayenga@arm.com for (ThreadID i = 0; i < numThreads; i++) { 5711567Smitch.hayenga@arm.com if (FullSystem) { 5811567Smitch.hayenga@arm.com thread = new Minor::MinorThread(this, i, params->system, 5911567Smitch.hayenga@arm.com params->itb, params->dtb, params->isa[i]); 6011567Smitch.hayenga@arm.com thread->setStatus(ThreadContext::Halted); 6111567Smitch.hayenga@arm.com } else { 6211567Smitch.hayenga@arm.com thread = new Minor::MinorThread(this, i, params->system, 6311567Smitch.hayenga@arm.com params->workload[i], params->itb, params->dtb, 6411567Smitch.hayenga@arm.com params->isa[i]); 6511567Smitch.hayenga@arm.com } 6611567Smitch.hayenga@arm.com 6711567Smitch.hayenga@arm.com threads.push_back(thread); 6811567Smitch.hayenga@arm.com ThreadContext *tc = thread->getTC(); 6911567Smitch.hayenga@arm.com threadContexts.push_back(tc); 7010259SAndrew.Bardsley@arm.com } 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.com if (params->checker) { 7410259SAndrew.Bardsley@arm.com fatal("The Minor model doesn't support checking (yet)\n"); 7510259SAndrew.Bardsley@arm.com } 7610259SAndrew.Bardsley@arm.com 7710259SAndrew.Bardsley@arm.com Minor::MinorDynInst::init(); 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com pipeline = new Minor::Pipeline(*this, *params); 8010259SAndrew.Bardsley@arm.com activityRecorder = pipeline->getActivityRecorder(); 8110259SAndrew.Bardsley@arm.com} 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.comMinorCPU::~MinorCPU() 8410259SAndrew.Bardsley@arm.com{ 8510259SAndrew.Bardsley@arm.com delete pipeline; 8610259SAndrew.Bardsley@arm.com 8710259SAndrew.Bardsley@arm.com for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) { 8810259SAndrew.Bardsley@arm.com delete threads[thread_id]; 8910259SAndrew.Bardsley@arm.com } 9010259SAndrew.Bardsley@arm.com} 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.comvoid 9310259SAndrew.Bardsley@arm.comMinorCPU::init() 9410259SAndrew.Bardsley@arm.com{ 9510259SAndrew.Bardsley@arm.com BaseCPU::init(); 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.com if (!params()->switched_out && 9810259SAndrew.Bardsley@arm.com system->getMemoryMode() != Enums::timing) 9910259SAndrew.Bardsley@arm.com { 10010259SAndrew.Bardsley@arm.com fatal("The Minor CPU requires the memory system to be in " 10110259SAndrew.Bardsley@arm.com "'timing' mode.\n"); 10210259SAndrew.Bardsley@arm.com } 10310259SAndrew.Bardsley@arm.com 10410259SAndrew.Bardsley@arm.com /* Initialise the ThreadContext's memory proxies */ 10510259SAndrew.Bardsley@arm.com for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) { 10610259SAndrew.Bardsley@arm.com ThreadContext *tc = getContext(thread_id); 10710259SAndrew.Bardsley@arm.com 10810259SAndrew.Bardsley@arm.com tc->initMemProxies(tc); 10910259SAndrew.Bardsley@arm.com } 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.com /* Initialise CPUs (== threads in the ISA) */ 11210259SAndrew.Bardsley@arm.com if (FullSystem && !params()->switched_out) { 11310259SAndrew.Bardsley@arm.com for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) 11410259SAndrew.Bardsley@arm.com { 11510259SAndrew.Bardsley@arm.com ThreadContext *tc = getContext(thread_id); 11610259SAndrew.Bardsley@arm.com 11710259SAndrew.Bardsley@arm.com /* Initialize CPU, including PC */ 11810259SAndrew.Bardsley@arm.com TheISA::initCPU(tc, cpuId()); 11910259SAndrew.Bardsley@arm.com } 12010259SAndrew.Bardsley@arm.com } 12110259SAndrew.Bardsley@arm.com} 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com/** Stats interface from SimObject (by way of BaseCPU) */ 12410259SAndrew.Bardsley@arm.comvoid 12510259SAndrew.Bardsley@arm.comMinorCPU::regStats() 12610259SAndrew.Bardsley@arm.com{ 12710259SAndrew.Bardsley@arm.com BaseCPU::regStats(); 12810259SAndrew.Bardsley@arm.com stats.regStats(name(), *this); 12910259SAndrew.Bardsley@arm.com pipeline->regStats(); 13010259SAndrew.Bardsley@arm.com} 13110259SAndrew.Bardsley@arm.com 13210259SAndrew.Bardsley@arm.comvoid 13310905Sandreas.sandberg@arm.comMinorCPU::serializeThread(CheckpointOut &cp, ThreadID thread_id) const 13410259SAndrew.Bardsley@arm.com{ 13510905Sandreas.sandberg@arm.com threads[thread_id]->serialize(cp); 13610259SAndrew.Bardsley@arm.com} 13710259SAndrew.Bardsley@arm.com 13810259SAndrew.Bardsley@arm.comvoid 13910905Sandreas.sandberg@arm.comMinorCPU::unserializeThread(CheckpointIn &cp, ThreadID thread_id) 14010259SAndrew.Bardsley@arm.com{ 14110905Sandreas.sandberg@arm.com threads[thread_id]->unserialize(cp); 14210259SAndrew.Bardsley@arm.com} 14310259SAndrew.Bardsley@arm.com 14410259SAndrew.Bardsley@arm.comvoid 14510905Sandreas.sandberg@arm.comMinorCPU::serialize(CheckpointOut &cp) const 14610259SAndrew.Bardsley@arm.com{ 14710905Sandreas.sandberg@arm.com pipeline->serialize(cp); 14810905Sandreas.sandberg@arm.com BaseCPU::serialize(cp); 14910259SAndrew.Bardsley@arm.com} 15010259SAndrew.Bardsley@arm.com 15110259SAndrew.Bardsley@arm.comvoid 15210905Sandreas.sandberg@arm.comMinorCPU::unserialize(CheckpointIn &cp) 15310259SAndrew.Bardsley@arm.com{ 15410905Sandreas.sandberg@arm.com pipeline->unserialize(cp); 15510905Sandreas.sandberg@arm.com BaseCPU::unserialize(cp); 15610259SAndrew.Bardsley@arm.com} 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.comAddr 15910259SAndrew.Bardsley@arm.comMinorCPU::dbg_vtophys(Addr addr) 16010259SAndrew.Bardsley@arm.com{ 16110259SAndrew.Bardsley@arm.com /* Note that this gives you the translation for thread 0 */ 16210259SAndrew.Bardsley@arm.com panic("No implementation for vtophy\n"); 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com return 0; 16510259SAndrew.Bardsley@arm.com} 16610259SAndrew.Bardsley@arm.com 16710259SAndrew.Bardsley@arm.comvoid 16811151Smitch.hayenga@arm.comMinorCPU::wakeup(ThreadID tid) 16910259SAndrew.Bardsley@arm.com{ 17011151Smitch.hayenga@arm.com DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid); 17111567Smitch.hayenga@arm.com assert(tid < numThreads); 17210259SAndrew.Bardsley@arm.com 17311567Smitch.hayenga@arm.com if (threads[tid]->status() == ThreadContext::Suspended) { 17411151Smitch.hayenga@arm.com threads[tid]->activate(); 17511567Smitch.hayenga@arm.com } 17610259SAndrew.Bardsley@arm.com} 17710259SAndrew.Bardsley@arm.com 17810259SAndrew.Bardsley@arm.comvoid 17910259SAndrew.Bardsley@arm.comMinorCPU::startup() 18010259SAndrew.Bardsley@arm.com{ 18110259SAndrew.Bardsley@arm.com DPRINTF(MinorCPU, "MinorCPU startup\n"); 18210259SAndrew.Bardsley@arm.com 18310259SAndrew.Bardsley@arm.com BaseCPU::startup(); 18410259SAndrew.Bardsley@arm.com 18510259SAndrew.Bardsley@arm.com for (auto i = threads.begin(); i != threads.end(); i ++) 18610259SAndrew.Bardsley@arm.com (*i)->startup(); 18710407Smitch.hayenga@arm.com 18811567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 18911567Smitch.hayenga@arm.com threads[tid]->startup(); 19011567Smitch.hayenga@arm.com pipeline->wakeupFetch(tid); 19111567Smitch.hayenga@arm.com } 19210259SAndrew.Bardsley@arm.com} 19310259SAndrew.Bardsley@arm.com 19410913Sandreas.sandberg@arm.comDrainState 19510913Sandreas.sandberg@arm.comMinorCPU::drain() 19610259SAndrew.Bardsley@arm.com{ 19710949Sandreas.sandberg@arm.com if (switchedOut()) { 19810949Sandreas.sandberg@arm.com DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n"); 19910949Sandreas.sandberg@arm.com return DrainState::Drained; 20010949Sandreas.sandberg@arm.com } 20110949Sandreas.sandberg@arm.com 20210259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU drain\n"); 20310259SAndrew.Bardsley@arm.com 20410259SAndrew.Bardsley@arm.com /* Need to suspend all threads and wait for Execute to idle. 20510259SAndrew.Bardsley@arm.com * Tell Fetch1 not to fetch */ 20610913Sandreas.sandberg@arm.com if (pipeline->drain()) { 20710259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU drained\n"); 20810913Sandreas.sandberg@arm.com return DrainState::Drained; 20910913Sandreas.sandberg@arm.com } else { 21010259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU not finished draining\n"); 21110913Sandreas.sandberg@arm.com return DrainState::Draining; 21210913Sandreas.sandberg@arm.com } 21310259SAndrew.Bardsley@arm.com} 21410259SAndrew.Bardsley@arm.com 21510259SAndrew.Bardsley@arm.comvoid 21610259SAndrew.Bardsley@arm.comMinorCPU::signalDrainDone() 21710259SAndrew.Bardsley@arm.com{ 21810259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU drain done\n"); 21910945Sandreas.sandberg@arm.com Drainable::signalDrainDone(); 22010259SAndrew.Bardsley@arm.com} 22110259SAndrew.Bardsley@arm.com 22210259SAndrew.Bardsley@arm.comvoid 22310259SAndrew.Bardsley@arm.comMinorCPU::drainResume() 22410259SAndrew.Bardsley@arm.com{ 22511499SIlias.Vougioukas@ARM.com /* When taking over from another cpu make sure lastStopped 22611499SIlias.Vougioukas@ARM.com * is reset since it might have not been defined previously 22711499SIlias.Vougioukas@ARM.com * and might lead to a stats corruption */ 22811499SIlias.Vougioukas@ARM.com pipeline->resetLastStopped(); 22911499SIlias.Vougioukas@ARM.com 23010259SAndrew.Bardsley@arm.com if (switchedOut()) { 23110259SAndrew.Bardsley@arm.com DPRINTF(Drain, "drainResume while switched out. Ignoring\n"); 23210259SAndrew.Bardsley@arm.com return; 23310259SAndrew.Bardsley@arm.com } 23410259SAndrew.Bardsley@arm.com 23510259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU drainResume\n"); 23610259SAndrew.Bardsley@arm.com 23710259SAndrew.Bardsley@arm.com if (!system->isTimingMode()) { 23810259SAndrew.Bardsley@arm.com fatal("The Minor CPU requires the memory system to be in " 23910259SAndrew.Bardsley@arm.com "'timing' mode.\n"); 24010259SAndrew.Bardsley@arm.com } 24110259SAndrew.Bardsley@arm.com 24211151Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24311151Smitch.hayenga@arm.com wakeup(tid); 24411567Smitch.hayenga@arm.com 24510259SAndrew.Bardsley@arm.com pipeline->drainResume(); 24610259SAndrew.Bardsley@arm.com} 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.comvoid 24910259SAndrew.Bardsley@arm.comMinorCPU::memWriteback() 25010259SAndrew.Bardsley@arm.com{ 25110259SAndrew.Bardsley@arm.com DPRINTF(Drain, "MinorCPU memWriteback\n"); 25210259SAndrew.Bardsley@arm.com} 25310259SAndrew.Bardsley@arm.com 25410259SAndrew.Bardsley@arm.comvoid 25510259SAndrew.Bardsley@arm.comMinorCPU::switchOut() 25610259SAndrew.Bardsley@arm.com{ 25710259SAndrew.Bardsley@arm.com DPRINTF(MinorCPU, "MinorCPU switchOut\n"); 25810259SAndrew.Bardsley@arm.com 25910259SAndrew.Bardsley@arm.com assert(!switchedOut()); 26010259SAndrew.Bardsley@arm.com BaseCPU::switchOut(); 26110259SAndrew.Bardsley@arm.com 26210259SAndrew.Bardsley@arm.com /* Check that the CPU is drained? */ 26310259SAndrew.Bardsley@arm.com activityRecorder->reset(); 26410259SAndrew.Bardsley@arm.com} 26510259SAndrew.Bardsley@arm.com 26610259SAndrew.Bardsley@arm.comvoid 26710259SAndrew.Bardsley@arm.comMinorCPU::takeOverFrom(BaseCPU *old_cpu) 26810259SAndrew.Bardsley@arm.com{ 26910259SAndrew.Bardsley@arm.com DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n"); 27010259SAndrew.Bardsley@arm.com 27110259SAndrew.Bardsley@arm.com BaseCPU::takeOverFrom(old_cpu); 27210259SAndrew.Bardsley@arm.com} 27310259SAndrew.Bardsley@arm.com 27410259SAndrew.Bardsley@arm.comvoid 27510407Smitch.hayenga@arm.comMinorCPU::activateContext(ThreadID thread_id) 27610259SAndrew.Bardsley@arm.com{ 27711567Smitch.hayenga@arm.com DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id); 27810259SAndrew.Bardsley@arm.com 27910259SAndrew.Bardsley@arm.com /* Do some cycle accounting. lastStopped is reset to stop the 28010259SAndrew.Bardsley@arm.com * wakeup call on the pipeline from adding the quiesce period 28110259SAndrew.Bardsley@arm.com * to BaseCPU::numCycles */ 28210407Smitch.hayenga@arm.com stats.quiesceCycles += pipeline->cyclesSinceLastStopped(); 28310407Smitch.hayenga@arm.com pipeline->resetLastStopped(); 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com /* Wake up the thread, wakeup the pipeline tick */ 28610407Smitch.hayenga@arm.com threads[thread_id]->activate(); 28710407Smitch.hayenga@arm.com wakeupOnEvent(Minor::Pipeline::CPUStageId); 28811567Smitch.hayenga@arm.com pipeline->wakeupFetch(thread_id); 28911526Sdavid.guillen@arm.com 29011526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_id); 29110259SAndrew.Bardsley@arm.com} 29210259SAndrew.Bardsley@arm.com 29310259SAndrew.Bardsley@arm.comvoid 29410259SAndrew.Bardsley@arm.comMinorCPU::suspendContext(ThreadID thread_id) 29510259SAndrew.Bardsley@arm.com{ 29610259SAndrew.Bardsley@arm.com DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id); 29710259SAndrew.Bardsley@arm.com 29810259SAndrew.Bardsley@arm.com threads[thread_id]->suspend(); 29911526Sdavid.guillen@arm.com 30011526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_id); 30110259SAndrew.Bardsley@arm.com} 30210259SAndrew.Bardsley@arm.com 30310259SAndrew.Bardsley@arm.comvoid 30410259SAndrew.Bardsley@arm.comMinorCPU::wakeupOnEvent(unsigned int stage_id) 30510259SAndrew.Bardsley@arm.com{ 30610259SAndrew.Bardsley@arm.com DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id); 30710259SAndrew.Bardsley@arm.com 30810259SAndrew.Bardsley@arm.com /* Mark that some activity has taken place and start the pipeline */ 30910259SAndrew.Bardsley@arm.com activityRecorder->activateStage(stage_id); 31010259SAndrew.Bardsley@arm.com pipeline->start(); 31110259SAndrew.Bardsley@arm.com} 31210259SAndrew.Bardsley@arm.com 31310259SAndrew.Bardsley@arm.comMinorCPU * 31410259SAndrew.Bardsley@arm.comMinorCPUParams::create() 31510259SAndrew.Bardsley@arm.com{ 31610259SAndrew.Bardsley@arm.com return new MinorCPU(this); 31710259SAndrew.Bardsley@arm.com} 31810259SAndrew.Bardsley@arm.com 31910259SAndrew.Bardsley@arm.comMasterPort &MinorCPU::getInstPort() 32010259SAndrew.Bardsley@arm.com{ 32110259SAndrew.Bardsley@arm.com return pipeline->getInstPort(); 32210259SAndrew.Bardsley@arm.com} 32310259SAndrew.Bardsley@arm.com 32410259SAndrew.Bardsley@arm.comMasterPort &MinorCPU::getDataPort() 32510259SAndrew.Bardsley@arm.com{ 32610259SAndrew.Bardsley@arm.com return pipeline->getDataPort(); 32710259SAndrew.Bardsley@arm.com} 32810259SAndrew.Bardsley@arm.com 32910259SAndrew.Bardsley@arm.comCounter 33010259SAndrew.Bardsley@arm.comMinorCPU::totalInsts() const 33110259SAndrew.Bardsley@arm.com{ 33210259SAndrew.Bardsley@arm.com Counter ret = 0; 33310259SAndrew.Bardsley@arm.com 33410259SAndrew.Bardsley@arm.com for (auto i = threads.begin(); i != threads.end(); i ++) 33510259SAndrew.Bardsley@arm.com ret += (*i)->numInst; 33610259SAndrew.Bardsley@arm.com 33710259SAndrew.Bardsley@arm.com return ret; 33810259SAndrew.Bardsley@arm.com} 33910259SAndrew.Bardsley@arm.com 34010259SAndrew.Bardsley@arm.comCounter 34110259SAndrew.Bardsley@arm.comMinorCPU::totalOps() const 34210259SAndrew.Bardsley@arm.com{ 34310259SAndrew.Bardsley@arm.com Counter ret = 0; 34410259SAndrew.Bardsley@arm.com 34510259SAndrew.Bardsley@arm.com for (auto i = threads.begin(); i != threads.end(); i ++) 34610259SAndrew.Bardsley@arm.com ret += (*i)->numOp; 34710259SAndrew.Bardsley@arm.com 34810259SAndrew.Bardsley@arm.com return ret; 34910259SAndrew.Bardsley@arm.com} 350