MinorCPU.py revision 13709:dd6b7ac5801f
112837Sgabeblack@google.com# Copyright (c) 2012-2014,2018 ARM Limited 212837Sgabeblack@google.com# All rights reserved. 312837Sgabeblack@google.com# 412837Sgabeblack@google.com# The license below extends only to copyright in the software and shall 512837Sgabeblack@google.com# not be construed as granting a license to any other intellectual 612837Sgabeblack@google.com# property including but not limited to intellectual property relating 712837Sgabeblack@google.com# to a hardware implementation of the functionality of the software 812837Sgabeblack@google.com# licensed hereunder. You may use the software subject to the license 912837Sgabeblack@google.com# terms below provided that you ensure that this notice is replicated 1012837Sgabeblack@google.com# unmodified and in its entirety in all distributions of the software, 1112837Sgabeblack@google.com# modified or unmodified, in source code or in binary form. 1212837Sgabeblack@google.com# 1312837Sgabeblack@google.com# Copyright (c) 2007 The Regents of The University of Michigan 1412837Sgabeblack@google.com# All rights reserved. 1512837Sgabeblack@google.com# 1612837Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 1712837Sgabeblack@google.com# modification, are permitted provided that the following conditions are 1812837Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 1912837Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 2012837Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 2112837Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 2212837Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 2312837Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 2412837Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 2512837Sgabeblack@google.com# this software without specific prior written permission. 2612837Sgabeblack@google.com# 2712837Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2812837Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2912837Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3012837Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3113041Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3212837Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3313251Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3412837Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3512837Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3612837Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3712837Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3813273Sgabeblack@google.com# 3913273Sgabeblack@google.com# Authors: Gabe Black 4012837Sgabeblack@google.com# Nathan Binkert 4112837Sgabeblack@google.com# Andrew Bardsley 4212837Sgabeblack@google.com 4313251Sgabeblack@google.comfrom __future__ import print_function 4413041Sgabeblack@google.com 4513041Sgabeblack@google.comfrom m5.defines import buildEnv 4612837Sgabeblack@google.comfrom m5.params import * 4712837Sgabeblack@google.comfrom m5.proxy import * 4812837Sgabeblack@google.comfrom m5.SimObject import SimObject 49from m5.objects.BaseCPU import BaseCPU 50from m5.objects.DummyChecker import DummyChecker 51from m5.objects.BranchPredictor import * 52from m5.objects.TimingExpr import TimingExpr 53 54from m5.objects.FuncUnit import OpClass 55 56class MinorOpClass(SimObject): 57 """Boxing of OpClass to get around build problems and provide a hook for 58 future additions to OpClass checks""" 59 60 type = 'MinorOpClass' 61 cxx_header = "cpu/minor/func_unit.hh" 62 63 opClass = Param.OpClass("op class to match") 64 65class MinorOpClassSet(SimObject): 66 """A set of matchable op classes""" 67 68 type = 'MinorOpClassSet' 69 cxx_header = "cpu/minor/func_unit.hh" 70 71 opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 72 " An empty list means any class") 73 74class MinorFUTiming(SimObject): 75 type = 'MinorFUTiming' 76 cxx_header = "cpu/minor/func_unit.hh" 77 78 mask = Param.UInt64(0, "mask for testing ExtMachInst") 79 match = Param.UInt64(0, "match value for testing ExtMachInst:" 80 " (ext_mach_inst & mask) == match") 81 suppress = Param.Bool(False, "if true, this inst. is not executed by" 82 " this FU") 83 extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 84 " this inst.") 85 extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 86 " run-time evaluated expression") 87 extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 88 " retire time for this insts dest registers once it leaves the" 89 " functional unit. For mem refs, if this is 0, the result's time" 90 " is marked as unpredictable and no forwarding can take place.") 91 srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 92 " after inst. issue that each src reg can be available for this" 93 " inst. to issue") 94 opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 95 "op classes to be considered for this decode. An empty set means any" 96 " class") 97 description = Param.String('', "description string of the decoding/inst." 98 " class") 99 100def minorMakeOpClassSet(op_classes): 101 """Make a MinorOpClassSet from a list of OpClass enum value strings""" 102 def boxOpClass(op_class): 103 return MinorOpClass(opClass=op_class) 104 105 return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ]) 106 107class MinorFU(SimObject): 108 type = 'MinorFU' 109 cxx_header = "cpu/minor/func_unit.hh" 110 111 opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 112 " allowed on this functional unit") 113 opLat = Param.Cycles(1, "latency in cycles") 114 issueLat = Param.Cycles(1, "cycles until another instruction can be" 115 " issued") 116 timings = VectorParam.MinorFUTiming([], "extra decoding rules") 117 118 cantForwardFromFUIndices = VectorParam.Unsigned([], 119 "list of FU indices from which this FU can't receive and early" 120 " (forwarded) result") 121 122class MinorFUPool(SimObject): 123 type = 'MinorFUPool' 124 cxx_header = "cpu/minor/func_unit.hh" 125 126 funcUnits = VectorParam.MinorFU("functional units") 127 128class MinorDefaultIntFU(MinorFU): 129 opClasses = minorMakeOpClassSet(['IntAlu']) 130 timings = [MinorFUTiming(description="Int", 131 srcRegsRelativeLats=[2])] 132 opLat = 3 133 134class MinorDefaultIntMulFU(MinorFU): 135 opClasses = minorMakeOpClassSet(['IntMult']) 136 timings = [MinorFUTiming(description='Mul', 137 srcRegsRelativeLats=[0])] 138 opLat = 3 139 140class MinorDefaultIntDivFU(MinorFU): 141 opClasses = minorMakeOpClassSet(['IntDiv']) 142 issueLat = 9 143 opLat = 9 144 145class MinorDefaultFloatSimdFU(MinorFU): 146 opClasses = minorMakeOpClassSet([ 147 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 148 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 149 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 150 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 151 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 152 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 153 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix', 154 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 155 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) 156 timings = [MinorFUTiming(description='FloatSimd', 157 srcRegsRelativeLats=[2])] 158 opLat = 6 159 160class MinorDefaultMemFU(MinorFU): 161 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 162 'FloatMemWrite']) 163 timings = [MinorFUTiming(description='Mem', 164 srcRegsRelativeLats=[1], extraAssumedLat=2)] 165 opLat = 1 166 167class MinorDefaultMiscFU(MinorFU): 168 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 169 opLat = 1 170 171class MinorDefaultFUPool(MinorFUPool): 172 funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 173 MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 174 MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 175 MinorDefaultMiscFU()] 176 177class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 178 179class MinorCPU(BaseCPU): 180 type = 'MinorCPU' 181 cxx_header = "cpu/minor/cpu.hh" 182 183 @classmethod 184 def memory_mode(cls): 185 return 'timing' 186 187 @classmethod 188 def require_caches(cls): 189 return True 190 191 @classmethod 192 def support_take_over(cls): 193 return True 194 195 threadPolicy = Param.ThreadPolicy('RoundRobin', 196 "Thread scheduling policy") 197 fetch1FetchLimit = Param.Unsigned(1, 198 "Number of line fetches allowable in flight at once") 199 fetch1LineSnapWidth = Param.Unsigned(0, 200 "Fetch1 'line' fetch snap size in bytes" 201 " (0 means use system cache line size)") 202 fetch1LineWidth = Param.Unsigned(0, 203 "Fetch1 maximum fetch size in bytes (0 means use system cache" 204 " line size)") 205 fetch1ToFetch2ForwardDelay = Param.Cycles(1, 206 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 207 fetch1ToFetch2BackwardDelay = Param.Cycles(1, 208 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 209 " signalling (0 means in the same cycle, 1 mean the next cycle)") 210 211 fetch2InputBufferSize = Param.Unsigned(2, 212 "Size of input buffer to Fetch2 in cycles-worth of insts.") 213 fetch2ToDecodeForwardDelay = Param.Cycles(1, 214 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 215 fetch2CycleInput = Param.Bool(True, 216 "Allow Fetch2 to cross input lines to generate full output each" 217 " cycle") 218 219 decodeInputBufferSize = Param.Unsigned(3, 220 "Size of input buffer to Decode in cycles-worth of insts.") 221 decodeToExecuteForwardDelay = Param.Cycles(1, 222 "Forward cycle delay from Decode to Execute (1 means next cycle)") 223 decodeInputWidth = Param.Unsigned(2, 224 "Width (in instructions) of input to Decode (and implicitly" 225 " Decode's own width)") 226 decodeCycleInput = Param.Bool(True, 227 "Allow Decode to pack instructions from more than one input cycle" 228 " to fill its output each cycle") 229 230 executeInputWidth = Param.Unsigned(2, 231 "Width (in instructions) of input to Execute") 232 executeCycleInput = Param.Bool(True, 233 "Allow Execute to use instructions from more than one input cycle" 234 " each cycle") 235 executeIssueLimit = Param.Unsigned(2, 236 "Number of issuable instructions in Execute each cycle") 237 executeMemoryIssueLimit = Param.Unsigned(1, 238 "Number of issuable memory instructions in Execute each cycle") 239 executeCommitLimit = Param.Unsigned(2, 240 "Number of committable instructions in Execute each cycle") 241 executeMemoryCommitLimit = Param.Unsigned(1, 242 "Number of committable memory references in Execute each cycle") 243 executeInputBufferSize = Param.Unsigned(7, 244 "Size of input buffer to Execute in cycles-worth of insts.") 245 executeMemoryWidth = Param.Unsigned(0, 246 "Width (and snap) in bytes of the data memory interface. (0 mean use" 247 " the system cacheLineSize)") 248 executeMaxAccessesInMemory = Param.Unsigned(2, 249 "Maximum number of concurrent accesses allowed to the memory system" 250 " from the dcache port") 251 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 252 "Maximum number of stores that the store buffer can issue per cycle") 253 executeLSQRequestsQueueSize = Param.Unsigned(1, 254 "Size of LSQ requests queue (address translation queue)") 255 executeLSQTransfersQueueSize = Param.Unsigned(2, 256 "Size of LSQ transfers queue (memory transaction queue)") 257 executeLSQStoreBufferSize = Param.Unsigned(5, 258 "Size of LSQ store buffer") 259 executeBranchDelay = Param.Cycles(1, 260 "Delay from Execute deciding to branch and Fetch1 reacting" 261 " (1 means next cycle)") 262 263 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 264 "FUlines for this processor") 265 266 executeSetTraceTimeOnCommit = Param.Bool(True, 267 "Set inst. trace times to be commit times") 268 executeSetTraceTimeOnIssue = Param.Bool(False, 269 "Set inst. trace times to be issue times") 270 271 executeAllowEarlyMemoryIssue = Param.Bool(True, 272 "Allow mem refs to be issued to the LSQ before reaching the head of" 273 " the in flight insts queue") 274 275 enableIdling = Param.Bool(True, 276 "Enable cycle skipping when the processor is idle\n"); 277 278 branchPred = Param.BranchPredictor(TournamentBP( 279 numThreads = Parent.numThreads), "Branch Predictor") 280 281 def addCheckerCpu(self): 282 print("Checker not yet supported by MinorCPU") 283 exit(1) 284