intr_control_noisa.cc revision 1762
14486Sbinkertn@umich.edu/* 27897Shestness@cs.utexas.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 34486Sbinkertn@umich.edu * All rights reserved. 44486Sbinkertn@umich.edu * 54486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144486Sbinkertn@umich.edu * this software without specific prior written permission. 154486Sbinkertn@umich.edu * 164486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu */ 284486Sbinkertn@umich.edu 297897Shestness@cs.utexas.edu#include <string> 304486Sbinkertn@umich.edu#include <vector> 3111988Sandreas.sandberg@arm.com 3211839SCurtis.Dunham@arm.com#include "cpu/base.hh" 333102SN/A#include "cpu/intr_control.hh" 343102SN/A#include "sim/builder.hh" 356654Snate@binkert.org#include "sim/sim_object.hh" 3610249Sstephan.diestelhorst@arm.com 378931Sandreas.hansson@arm.comusing namespace std; 382212SN/A 399524SAndreas.Sandberg@ARM.comIntrControl::IntrControl(const string &name, BaseCPU *c) 409524SAndreas.Sandberg@ARM.com : SimObject(name), cpu(c) 412902SN/A{} 428703Sandreas.hansson@arm.com 431783SN/A/* @todo 449338SAndreas.Sandberg@arm.com *Fix the cpu sim object parameter to be a system pointer 458839Sandreas.hansson@arm.com *instead, to avoid some extra dereferencing 467673Snate@binkert.org */ 4711988Sandreas.sandberg@arm.comvoid 4811988Sandreas.sandberg@arm.comIntrControl::post(int int_num, int index) 4911988Sandreas.sandberg@arm.com{ 5011988Sandreas.sandberg@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 514859Snate@binkert.org BaseCPU *temp = xcvec[0]->cpu; 528931Sandreas.hansson@arm.com temp->post_interrupt(int_num, index); 538931Sandreas.hansson@arm.com} 542902SN/A 559408Sandreas.hansson@arm.comvoid 5611420Sdavid.guillen@arm.comIntrControl::post(int cpu_id, int int_num, int index) 5711420Sdavid.guillen@arm.com{ 5811420Sdavid.guillen@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 5911420Sdavid.guillen@arm.com BaseCPU *temp = xcvec[cpu_id]->cpu; 6010700Sandreas.hansson@arm.com temp->post_interrupt(int_num, index); 6110700Sandreas.hansson@arm.com} 6211838SCurtis.Dunham@arm.com 6310700Sandreas.hansson@arm.comvoid 6410700Sandreas.hansson@arm.comIntrControl::clear(int int_num, int index) 6510700Sandreas.hansson@arm.com{ 6610700Sandreas.hansson@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 679408Sandreas.hansson@arm.com BaseCPU *temp = xcvec[0]->cpu; 689408Sandreas.hansson@arm.com temp->clear_interrupt(int_num, index); 699408Sandreas.hansson@arm.com} 709408Sandreas.hansson@arm.com 719408Sandreas.hansson@arm.comvoid 729814Sandreas.hansson@arm.comIntrControl::clear(int cpu_id, int int_num, int index) 739814Sandreas.hansson@arm.com{ 7411273Sandreas.sandberg@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 7511270Sandreas.sandberg@arm.com BaseCPU *temp = xcvec[cpu_id]->cpu; 767914SBrad.Beckmann@amd.com temp->clear_interrupt(int_num, index); 778666SPrakash.Ramrakhyani@arm.com} 787914SBrad.Beckmann@amd.com 797914SBrad.Beckmann@amd.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 807914SBrad.Beckmann@amd.com 817914SBrad.Beckmann@amd.com SimObjectParam<BaseCPU *> cpu; 827914SBrad.Beckmann@amd.com 837914SBrad.Beckmann@amd.comEND_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 847914SBrad.Beckmann@amd.com 857914SBrad.Beckmann@amd.comBEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 867914SBrad.Beckmann@amd.com 877914SBrad.Beckmann@amd.com INIT_PARAM(cpu, "the cpu") 887914SBrad.Beckmann@amd.com 897914SBrad.Beckmann@amd.comEND_INIT_SIM_OBJECT_PARAMS(IntrControl) 907914SBrad.Beckmann@amd.com 918769Sgblack@eecs.umich.eduCREATE_SIM_OBJECT(IntrControl) 928769Sgblack@eecs.umich.edu{ 938769Sgblack@eecs.umich.edu return new IntrControl(getInstanceName(), cpu); 9410282Sdam.sunwoo@arm.com} 9510282Sdam.sunwoo@arm.com 968769Sgblack@eecs.umich.eduREGISTER_SIM_OBJECT("IntrControl", IntrControl) 978769Sgblack@eecs.umich.edu