exetrace.hh revision 2665:a124942bacb8 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __EXETRACE_HH__
33#define __EXETRACE_HH__
34
35#include <fstream>
36#include <vector>
37
38#include "sim/host.hh"
39#include "cpu/inst_seq.hh"	// for InstSeqNum
40#include "base/trace.hh"
41#include "cpu/exec_context.hh"
42#include "cpu/static_inst.hh"
43
44class BaseCPU;
45
46
47namespace Trace {
48
49class InstRecord : public Record
50{
51  protected:
52    typedef TheISA::IntRegFile IntRegFile;
53
54    // The following fields are initialized by the constructor and
55    // thus guaranteed to be valid.
56    BaseCPU *cpu;
57    // need to make this ref-counted so it doesn't go away before we
58    // dump the record
59    StaticInstPtr staticInst;
60    Addr PC;
61    bool misspeculating;
62    unsigned thread;
63
64    // The remaining fields are only valid for particular instruction
65    // types (e.g, addresses for memory ops) or when particular
66    // options are enabled (e.g., tracing full register contents).
67    // Each data field has an associated valid flag to indicate
68    // whether the data field is valid.
69    Addr addr;
70    bool addr_valid;
71
72    union {
73        uint64_t as_int;
74        double as_double;
75    } data;
76    enum {
77        DataInvalid = 0,
78        DataInt8 = 1,	// set to equal number of bytes
79        DataInt16 = 2,
80        DataInt32 = 4,
81        DataInt64 = 8,
82        DataDouble = 3
83    } data_status;
84
85    InstSeqNum fetch_seq;
86    bool fetch_seq_valid;
87
88    InstSeqNum cp_seq;
89    bool cp_seq_valid;
90
91    struct iRegFile {
92        IntRegFile regs;
93    };
94    iRegFile *iregs;
95    bool regs_valid;
96
97  public:
98    InstRecord(Tick _cycle, BaseCPU *_cpu,
99               const StaticInstPtr &_staticInst,
100               Addr _pc, bool spec, int _thread)
101        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
102          misspeculating(spec), thread(_thread)
103    {
104        data_status = DataInvalid;
105        addr_valid = false;
106        regs_valid = false;
107
108        fetch_seq_valid = false;
109        cp_seq_valid = false;
110    }
111
112    virtual ~InstRecord() { }
113
114    virtual void dump(std::ostream &outs);
115
116    void setAddr(Addr a) { addr = a; addr_valid = true; }
117
118    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
119    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
120    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
121    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
122
123    void setData(int64_t d) { setData((uint64_t)d); }
124    void setData(int32_t d) { setData((uint32_t)d); }
125    void setData(int16_t d) { setData((uint16_t)d); }
126    void setData(int8_t d)  { setData((uint8_t)d); }
127
128    void setData(double d) { data.as_double = d; data_status = DataDouble; }
129
130    void setFetchSeq(InstSeqNum seq)
131    { fetch_seq = seq; fetch_seq_valid = true; }
132
133    void setCPSeq(InstSeqNum seq)
134    { cp_seq = seq; cp_seq_valid = true; }
135
136    void setRegs(const IntRegFile &regs);
137
138    void finalize() { theLog.append(this); }
139
140    enum InstExecFlagBits {
141        TRACE_MISSPEC = 0,
142        PRINT_CYCLE,
143        PRINT_OP_CLASS,
144        PRINT_THREAD_NUM,
145        PRINT_RESULT_DATA,
146        PRINT_EFF_ADDR,
147        PRINT_INT_REGS,
148        PRINT_FETCH_SEQ,
149        PRINT_CP_SEQ,
150        INTEL_FORMAT,
151        NUM_BITS
152    };
153
154    static std::vector<bool> flags;
155    static std::string trace_system;
156
157    static void setParams();
158
159    static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
160};
161
162
163inline void
164InstRecord::setRegs(const IntRegFile &regs)
165{
166    if (!iregs)
167      iregs = new iRegFile;
168
169    memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
170    regs_valid = true;
171}
172
173inline
174InstRecord *
175getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
176              const StaticInstPtr staticInst,
177              Addr pc, int thread = 0)
178{
179    if (DTRACE(InstExec) &&
180        (InstRecord::traceMisspec() || !xc->misspeculating())) {
181        return new InstRecord(cycle, cpu, staticInst, pc,
182                              xc->misspeculating(), thread);
183    }
184
185    return NULL;
186}
187
188
189}
190
191#endif // __EXETRACE_HH__
192