exetrace.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __EXETRACE_HH__
30#define __EXETRACE_HH__
31
32#include <fstream>
33#include <vector>
34
35#include "sim/host.hh"
36#include "cpu/inst_seq.hh"	// for InstSeqNum
37#include "base/trace.hh"
38#include "cpu/exec_context.hh"
39#include "cpu/static_inst.hh"
40
41class BaseCPU;
42
43
44namespace Trace {
45
46class InstRecord : public Record
47{
48  protected:
49    typedef TheISA::IntRegFile IntRegFile;
50
51    // The following fields are initialized by the constructor and
52    // thus guaranteed to be valid.
53    BaseCPU *cpu;
54    // need to make this ref-counted so it doesn't go away before we
55    // dump the record
56    StaticInstPtr staticInst;
57    Addr PC;
58    bool misspeculating;
59    unsigned thread;
60
61    // The remaining fields are only valid for particular instruction
62    // types (e.g, addresses for memory ops) or when particular
63    // options are enabled (e.g., tracing full register contents).
64    // Each data field has an associated valid flag to indicate
65    // whether the data field is valid.
66    Addr addr;
67    bool addr_valid;
68
69    union {
70        uint64_t as_int;
71        double as_double;
72    } data;
73    enum {
74        DataInvalid = 0,
75        DataInt8 = 1,	// set to equal number of bytes
76        DataInt16 = 2,
77        DataInt32 = 4,
78        DataInt64 = 8,
79        DataDouble = 3
80    } data_status;
81
82    InstSeqNum fetch_seq;
83    bool fetch_seq_valid;
84
85    InstSeqNum cp_seq;
86    bool cp_seq_valid;
87
88    struct iRegFile {
89        IntRegFile regs;
90    };
91    iRegFile *iregs;
92    bool regs_valid;
93
94  public:
95    InstRecord(Tick _cycle, BaseCPU *_cpu,
96               const StaticInstPtr &_staticInst,
97               Addr _pc, bool spec, int _thread)
98        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
99          misspeculating(spec), thread(_thread)
100    {
101        data_status = DataInvalid;
102        addr_valid = false;
103        regs_valid = false;
104
105        fetch_seq_valid = false;
106        cp_seq_valid = false;
107    }
108
109    virtual ~InstRecord() { }
110
111    virtual void dump(std::ostream &outs);
112
113    void setAddr(Addr a) { addr = a; addr_valid = true; }
114
115    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
116    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
117    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
118    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
119
120    void setData(int64_t d) { setData((uint64_t)d); }
121    void setData(int32_t d) { setData((uint32_t)d); }
122    void setData(int16_t d) { setData((uint16_t)d); }
123    void setData(int8_t d)  { setData((uint8_t)d); }
124
125    void setData(double d) { data.as_double = d; data_status = DataDouble; }
126
127    void setFetchSeq(InstSeqNum seq)
128    { fetch_seq = seq; fetch_seq_valid = true; }
129
130    void setCPSeq(InstSeqNum seq)
131    { cp_seq = seq; cp_seq_valid = true; }
132
133    void setRegs(const IntRegFile &regs);
134
135    void finalize() { theLog.append(this); }
136
137    enum InstExecFlagBits {
138        TRACE_MISSPEC = 0,
139        PRINT_CYCLE,
140        PRINT_OP_CLASS,
141        PRINT_THREAD_NUM,
142        PRINT_RESULT_DATA,
143        PRINT_EFF_ADDR,
144        PRINT_INT_REGS,
145        PRINT_FETCH_SEQ,
146        PRINT_CP_SEQ,
147        INTEL_FORMAT,
148        NUM_BITS
149    };
150
151    static std::vector<bool> flags;
152    static std::string trace_system;
153
154    static void setParams();
155
156    static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
157};
158
159
160inline void
161InstRecord::setRegs(const IntRegFile &regs)
162{
163    if (!iregs)
164      iregs = new iRegFile;
165
166    memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
167    regs_valid = true;
168}
169
170inline
171InstRecord *
172getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
173              const StaticInstPtr staticInst,
174              Addr pc, int thread = 0)
175{
176    if (DTRACE(InstExec) &&
177        (InstRecord::traceMisspec() || !xc->misspeculating())) {
178        return new InstRecord(cycle, cpu, staticInst, pc,
179                              xc->misspeculating(), thread);
180    }
181
182    return NULL;
183}
184
185
186}
187
188#endif // __EXETRACE_HH__
189