exetrace.hh revision 4054
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#ifndef __EXETRACE_HH__ 332SN/A#define __EXETRACE_HH__ 342SN/A 353918Ssaidi@eecs.umich.edu#include <cstring> 362SN/A#include <fstream> 372SN/A#include <vector> 382SN/A 394046Sbinkertn@umich.edu#include "base/trace.hh" 404046Sbinkertn@umich.edu#include "cpu/inst_seq.hh" // for InstSeqNum 414046Sbinkertn@umich.edu#include "cpu/static_inst.hh" 424046Sbinkertn@umich.edu#include "cpu/thread_context.hh" 4356SN/A#include "sim/host.hh" 442SN/A 453064Sgblack@eecs.umich.educlass ThreadContext; 462SN/A 472SN/A 482SN/Anamespace Trace { 492SN/A 504046Sbinkertn@umich.educlass InstRecord 512SN/A{ 522SN/A protected: 532107SN/A typedef TheISA::IntRegFile IntRegFile; 542SN/A 554046Sbinkertn@umich.edu Tick when; 564046Sbinkertn@umich.edu 572SN/A // The following fields are initialized by the constructor and 582SN/A // thus guaranteed to be valid. 593064Sgblack@eecs.umich.edu ThreadContext *thread; 602SN/A // need to make this ref-counted so it doesn't go away before we 612SN/A // dump the record 622107SN/A StaticInstPtr staticInst; 632SN/A Addr PC; 642SN/A bool misspeculating; 652SN/A 662SN/A // The remaining fields are only valid for particular instruction 672SN/A // types (e.g, addresses for memory ops) or when particular 682SN/A // options are enabled (e.g., tracing full register contents). 692SN/A // Each data field has an associated valid flag to indicate 702SN/A // whether the data field is valid. 712SN/A Addr addr; 722SN/A bool addr_valid; 732SN/A 742SN/A union { 752SN/A uint64_t as_int; 762SN/A double as_double; 772SN/A } data; 782SN/A enum { 792SN/A DataInvalid = 0, 802SN/A DataInt8 = 1, // set to equal number of bytes 812SN/A DataInt16 = 2, 822SN/A DataInt32 = 4, 832SN/A DataInt64 = 8, 842SN/A DataDouble = 3 852SN/A } data_status; 862SN/A 872SN/A InstSeqNum fetch_seq; 882SN/A bool fetch_seq_valid; 892SN/A 902SN/A InstSeqNum cp_seq; 912SN/A bool cp_seq_valid; 922SN/A 932SN/A struct iRegFile { 942SN/A IntRegFile regs; 952SN/A }; 962SN/A iRegFile *iregs; 972SN/A bool regs_valid; 982SN/A 992SN/A public: 1004046Sbinkertn@umich.edu InstRecord(Tick _when, ThreadContext *_thread, 1012107SN/A const StaticInstPtr &_staticInst, 1023064Sgblack@eecs.umich.edu Addr _pc, bool spec) 1034046Sbinkertn@umich.edu : when(_when), thread(_thread), 1043064Sgblack@eecs.umich.edu staticInst(_staticInst), PC(_pc), 1053064Sgblack@eecs.umich.edu misspeculating(spec) 1062SN/A { 1072SN/A data_status = DataInvalid; 1082SN/A addr_valid = false; 1092SN/A regs_valid = false; 1102SN/A 1112SN/A fetch_seq_valid = false; 1122SN/A cp_seq_valid = false; 1132SN/A } 1142SN/A 1154046Sbinkertn@umich.edu ~InstRecord() { } 1162SN/A 1172SN/A void setAddr(Addr a) { addr = a; addr_valid = true; } 1182SN/A 1192SN/A void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 1202SN/A void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 1212SN/A void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 1222SN/A void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 1232SN/A 1242SN/A void setData(int64_t d) { setData((uint64_t)d); } 1252SN/A void setData(int32_t d) { setData((uint32_t)d); } 1262SN/A void setData(int16_t d) { setData((uint16_t)d); } 1272SN/A void setData(int8_t d) { setData((uint8_t)d); } 1282SN/A 1292SN/A void setData(double d) { data.as_double = d; data_status = DataDouble; } 1302SN/A 1312SN/A void setFetchSeq(InstSeqNum seq) 1322SN/A { fetch_seq = seq; fetch_seq_valid = true; } 1332SN/A 1342SN/A void setCPSeq(InstSeqNum seq) 1352SN/A { cp_seq = seq; cp_seq_valid = true; } 1362SN/A 1372SN/A void setRegs(const IntRegFile ®s); 1382SN/A 1394046Sbinkertn@umich.edu void dump(); 1402SN/A}; 1412SN/A 1422SN/A 1432SN/Ainline void 1442SN/AInstRecord::setRegs(const IntRegFile ®s) 1452SN/A{ 1462SN/A if (!iregs) 1472SN/A iregs = new iRegFile; 1482SN/A 1493918Ssaidi@eecs.umich.edu std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); 1502SN/A regs_valid = true; 1512SN/A} 1522SN/A 1534054Sbinkertn@umich.eduinline InstRecord * 1544054Sbinkertn@umich.edugetInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, 1553064Sgblack@eecs.umich.edu Addr pc) 1562SN/A{ 1574054Sbinkertn@umich.edu if (!IsOn(ExecEnable)) 1584054Sbinkertn@umich.edu return NULL; 1592SN/A 1604054Sbinkertn@umich.edu if (!IsOn(ExecSpeculative) && tc->misspeculating()) 1614054Sbinkertn@umich.edu return NULL; 1624054Sbinkertn@umich.edu 1634054Sbinkertn@umich.edu return new InstRecord(when, tc, staticInst, pc, tc->misspeculating()); 1642SN/A} 1652SN/A 1664054Sbinkertn@umich.edu/* namespace Trace */ } 1672SN/A 1682SN/A#endif // __EXETRACE_HH__ 169