exetrace.hh revision 1762 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __EXETRACE_HH__
30#define __EXETRACE_HH__
31
32#include <fstream>
33#include <vector>
34
35#include "sim/host.hh"
36#include "cpu/inst_seq.hh"	// for InstSeqNum
37#include "base/trace.hh"
38#include "cpu/exec_context.hh"
39#include "cpu/static_inst.hh"
40
41class BaseCPU;
42
43
44namespace Trace {
45
46class InstRecord : public Record
47{
48  protected:
49
50    // The following fields are initialized by the constructor and
51    // thus guaranteed to be valid.
52    BaseCPU *cpu;
53    // need to make this ref-counted so it doesn't go away before we
54    // dump the record
55    StaticInstPtr<TheISA> staticInst;
56    Addr PC;
57    bool misspeculating;
58    unsigned thread;
59
60    // The remaining fields are only valid for particular instruction
61    // types (e.g, addresses for memory ops) or when particular
62    // options are enabled (e.g., tracing full register contents).
63    // Each data field has an associated valid flag to indicate
64    // whether the data field is valid.
65    Addr addr;
66    bool addr_valid;
67
68    union {
69        uint64_t as_int;
70        double as_double;
71    } data;
72    enum {
73        DataInvalid = 0,
74        DataInt8 = 1,	// set to equal number of bytes
75        DataInt16 = 2,
76        DataInt32 = 4,
77        DataInt64 = 8,
78        DataDouble = 3
79    } data_status;
80
81    InstSeqNum fetch_seq;
82    bool fetch_seq_valid;
83
84    InstSeqNum cp_seq;
85    bool cp_seq_valid;
86
87    struct iRegFile {
88        IntRegFile regs;
89    };
90    iRegFile *iregs;
91    bool regs_valid;
92
93  public:
94    InstRecord(Tick _cycle, BaseCPU *_cpu,
95               const StaticInstPtr<TheISA> &_staticInst,
96               Addr _pc, bool spec, int _thread)
97        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
98          misspeculating(spec), thread(_thread)
99    {
100        data_status = DataInvalid;
101        addr_valid = false;
102        regs_valid = false;
103
104        fetch_seq_valid = false;
105        cp_seq_valid = false;
106    }
107
108    virtual ~InstRecord() { }
109
110    virtual void dump(std::ostream &outs);
111
112    void setAddr(Addr a) { addr = a; addr_valid = true; }
113
114    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
115    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
116    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
117    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
118
119    void setData(int64_t d) { setData((uint64_t)d); }
120    void setData(int32_t d) { setData((uint32_t)d); }
121    void setData(int16_t d) { setData((uint16_t)d); }
122    void setData(int8_t d)  { setData((uint8_t)d); }
123
124    void setData(double d) { data.as_double = d; data_status = DataDouble; }
125
126    void setFetchSeq(InstSeqNum seq)
127    { fetch_seq = seq; fetch_seq_valid = true; }
128
129    void setCPSeq(InstSeqNum seq)
130    { cp_seq = seq; cp_seq_valid = true; }
131
132    void setRegs(const IntRegFile &regs);
133
134    void finalize() { theLog.append(this); }
135
136    enum InstExecFlagBits {
137        TRACE_MISSPEC = 0,
138        PRINT_CYCLE,
139        PRINT_OP_CLASS,
140        PRINT_THREAD_NUM,
141        PRINT_RESULT_DATA,
142        PRINT_EFF_ADDR,
143        PRINT_INT_REGS,
144        PRINT_FETCH_SEQ,
145        PRINT_CP_SEQ,
146        NUM_BITS
147    };
148
149    static std::vector<bool> flags;
150
151    static void setParams();
152
153    static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
154};
155
156
157inline void
158InstRecord::setRegs(const IntRegFile &regs)
159{
160    if (!iregs)
161      iregs = new iRegFile;
162
163    memcpy(&iregs->regs, regs, sizeof(IntRegFile));
164    regs_valid = true;
165}
166
167inline
168InstRecord *
169getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
170              const StaticInstPtr<TheISA> staticInst,
171              Addr pc, int thread = 0)
172{
173    if (DTRACE(InstExec) &&
174        (InstRecord::traceMisspec() || !xc->misspeculating())) {
175        return new InstRecord(cycle, cpu, staticInst, pc,
176                              xc->misspeculating(), thread);
177    }
178
179    return NULL;
180}
181
182
183}
184
185#endif // __EXETRACE_HH__
186