exetrace.cc revision 5947
12155SN/A/*
22155SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32155SN/A * All rights reserved.
42155SN/A *
52155SN/A * Redistribution and use in source and binary forms, with or without
62155SN/A * modification, are permitted provided that the following conditions are
72155SN/A * met: redistributions of source code must retain the above copyright
82155SN/A * notice, this list of conditions and the following disclaimer;
92155SN/A * redistributions in binary form must reproduce the above copyright
102155SN/A * notice, this list of conditions and the following disclaimer in the
112155SN/A * documentation and/or other materials provided with the distribution;
122155SN/A * neither the name of the copyright holders nor the names of its
132155SN/A * contributors may be used to endorse or promote products derived from
142155SN/A * this software without specific prior written permission.
152155SN/A *
162155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272155SN/A *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Lisa Hsu
302155SN/A *          Nathan Binkert
314202Sbinkertn@umich.edu *          Steve Raasch
322155SN/A */
339850Sandreas.hansson@arm.com
349850Sandreas.hansson@arm.com#include <iomanip>
359850Sandreas.hansson@arm.com
367768SAli.Saidi@ARM.com#include "base/loader/symtab.hh"
377768SAli.Saidi@ARM.com#include "cpu/base.hh"
3810695SAli.Saidi@ARM.com#include "cpu/exetrace.hh"
3910695SAli.Saidi@ARM.com#include "cpu/static_inst.hh"
4010695SAli.Saidi@ARM.com#include "cpu/thread_context.hh"
4110695SAli.Saidi@ARM.com#include "enums/OpClass.hh"
4210695SAli.Saidi@ARM.com
438887Sgeoffrey.blake@arm.comusing namespace std;
442766Sktlim@umich.eduusing namespace TheISA;
454486Sbinkertn@umich.edu
4610663SAli.Saidi@ARM.comnamespace Trace {
474486Sbinkertn@umich.edu
488739Sgblack@eecs.umich.eduvoid
4910259SAndrew.Bardsley@arm.comExeTracerRecord::dumpTicks(ostream &outs)
504486Sbinkertn@umich.edu{
514202Sbinkertn@umich.edu    ccprintf(outs, "%7d: ", when);
524202Sbinkertn@umich.edu}
534202Sbinkertn@umich.edu
544202Sbinkertn@umich.eduvoid
5510319SAndreas.Sandberg@ARM.comTrace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
564202Sbinkertn@umich.edu{
574776Sgblack@eecs.umich.edu    ostream &outs = Trace::output();
588739Sgblack@eecs.umich.edu
596365Sgblack@eecs.umich.edu    if (IsOn(ExecTicks))
604202Sbinkertn@umich.edu        dumpTicks(outs);
618777Sgblack@eecs.umich.edu
624202Sbinkertn@umich.edu    outs << thread->getCpuPtr()->name() << " ";
639913Ssteve.reinhardt@amd.com
644202Sbinkertn@umich.edu    if (IsOn(ExecSpeculative))
654202Sbinkertn@umich.edu        outs << (misspeculating ? "-" : "+") << " ";
665217Ssaidi@eecs.umich.edu
674202Sbinkertn@umich.edu    if (IsOn(ExecThread))
6810259SAndrew.Bardsley@arm.com        outs << "T" << thread->threadId() << " : ";
692155SN/A
708887Sgeoffrey.blake@arm.com    std::string sym_str;
7110201SAndrew.Bardsley@arm.com    Addr sym_addr;
728887Sgeoffrey.blake@arm.com    if (debugSymbolTable
739340SAndreas.Sandberg@arm.com        && IsOn(ExecSymbol)
748887Sgeoffrey.blake@arm.com#if FULL_SYSTEM
755192Ssaidi@eecs.umich.edu        && !inUserMode(thread)
768335Snate@binkert.org#endif
778335Snate@binkert.org        && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
788335Snate@binkert.org        if (PC != sym_addr)
798335Snate@binkert.org            sym_str += csprintf("+%d", PC - sym_addr);
808335Snate@binkert.org        outs << "@" << sym_str;
819534SAndreas.Sandberg@ARM.com    }
829534SAndreas.Sandberg@ARM.com    else {
839534SAndreas.Sandberg@ARM.com        outs << "0x" << hex << PC;
848335Snate@binkert.org    }
859534SAndreas.Sandberg@ARM.com
869534SAndreas.Sandberg@ARM.com    if (inst->isMicroop()) {
878335Snate@binkert.org        outs << "." << setw(2) << dec << upc;
889534SAndreas.Sandberg@ARM.com    } else {
899534SAndreas.Sandberg@ARM.com        outs << "   ";
909534SAndreas.Sandberg@ARM.com    }
919534SAndreas.Sandberg@ARM.com
929534SAndreas.Sandberg@ARM.com    outs << " : ";
939534SAndreas.Sandberg@ARM.com
949534SAndreas.Sandberg@ARM.com    //
959534SAndreas.Sandberg@ARM.com    //  Print decoded instruction
969534SAndreas.Sandberg@ARM.com    //
9710383Smitch.hayenga@arm.com
988335Snate@binkert.org    outs << setw(26) << left;
998335Snate@binkert.org    outs << inst->disassemble(PC, debugSymbolTable);
1008471SGiacomo.Gabrielli@arm.com
1018335Snate@binkert.org    if (ran) {
1028335Snate@binkert.org        outs << " : ";
10310529Smorr@cs.wisc.edu
1045192Ssaidi@eecs.umich.edu        if (IsOn(ExecOpClass)) {
1058232Snate@binkert.org            outs << Enums::OpClassStrings[inst->opClass()] << " : ";
1068232Snate@binkert.org        }
10710664SAli.Saidi@ARM.com
1088300Schander.sudanthi@arm.com        if (IsOn(ExecResult) && data_status != DataInvalid) {
10910383Smitch.hayenga@arm.com            ccprintf(outs, " D=%#018x", data.as_int);
1105192Ssaidi@eecs.umich.edu        }
11111162Ssteve.reinhardt@amd.com
11211162Ssteve.reinhardt@amd.com        if (IsOn(ExecEffAddr) && addr_valid)
11311162Ssteve.reinhardt@amd.com            outs << " A=0x" << hex << addr;
11411162Ssteve.reinhardt@amd.com
1158300Schander.sudanthi@arm.com        if (IsOn(ExecFetchSeq) && fetch_seq_valid)
116            outs << "  FetchSeq=" << dec << fetch_seq;
117
118        if (IsOn(ExecCPSeq) && cp_seq_valid)
119            outs << "  CPSeq=" << dec << cp_seq;
120    }
121
122    //
123    //  End of line...
124    //
125    outs << endl;
126}
127
128void
129Trace::ExeTracerRecord::dump()
130{
131    /*
132     * The behavior this check tries to achieve is that if ExecMacro is on,
133     * the macroop will be printed. If it's on and microops are also on, it's
134     * printed before the microops start printing to give context. If the
135     * microops aren't printed, then it's printed only when the final microop
136     * finishes. Macroops then behave like regular instructions and don't
137     * complete/print when they fault.
138     */
139    if (IsOn(ExecMacro) && staticInst->isMicroop() &&
140            ((IsOn(ExecMicro) &&
141             macroStaticInst && staticInst->isFirstMicroop()) ||
142            (!IsOn(ExecMicro) &&
143             macroStaticInst && staticInst->isLastMicroop()))) {
144        traceInst(macroStaticInst, false);
145    }
146    if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
147        traceInst(staticInst, true);
148    }
149}
150
151/* namespace Trace */ }
152
153////////////////////////////////////////////////////////////////////////
154//
155//  ExeTracer Simulation Object
156//
157Trace::ExeTracer *
158ExeTracerParams::create()
159{
160    return new Trace::ExeTracer(this);
161};
162