exetrace.cc revision 5866:303e409d88d9
17119SN/A/* 27119SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 37119SN/A * All rights reserved. 47119SN/A * 57119SN/A * Redistribution and use in source and binary forms, with or without 67119SN/A * modification, are permitted provided that the following conditions are 77119SN/A * met: redistributions of source code must retain the above copyright 87119SN/A * notice, this list of conditions and the following disclaimer; 97119SN/A * redistributions in binary form must reproduce the above copyright 107119SN/A * notice, this list of conditions and the following disclaimer in the 117119SN/A * documentation and/or other materials provided with the distribution; 127119SN/A * neither the name of the copyright holders nor the names of its 137119SN/A * contributors may be used to endorse or promote products derived from 147119SN/A * this software without specific prior written permission. 157119SN/A * 167119SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177119SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187119SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197119SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207119SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217119SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227119SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237119SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247119SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257119SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267119SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277119SN/A * 287119SN/A * Authors: Steve Reinhardt 297119SN/A * Lisa Hsu 307119SN/A * Nathan Binkert 317119SN/A * Steve Raasch 327119SN/A */ 337119SN/A 347119SN/A#include <iomanip> 357119SN/A 367119SN/A#include "base/loader/symtab.hh" 377119SN/A#include "cpu/base.hh" 387119SN/A#include "cpu/exetrace.hh" 397119SN/A#include "cpu/static_inst.hh" 407119SN/A#include "cpu/thread_context.hh" 417119SN/A#include "enums/OpClass.hh" 427119SN/A 437119SN/Ausing namespace std; 447119SN/Ausing namespace TheISA; 457119SN/A 467590Sgblack@eecs.umich.edunamespace Trace { 477590Sgblack@eecs.umich.edu 487119SN/Avoid 497590Sgblack@eecs.umich.eduExeTracerRecord::dumpTicks(ostream &outs) 508069SMatt.Horsnell@arm.com{ 518069SMatt.Horsnell@arm.com ccprintf(outs, "%7d: ", when); 527590Sgblack@eecs.umich.edu} 537590Sgblack@eecs.umich.edu 547590Sgblack@eecs.umich.eduvoid 557590Sgblack@eecs.umich.eduTrace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) 567590Sgblack@eecs.umich.edu{ 577590Sgblack@eecs.umich.edu ostream &outs = Trace::output(); 587590Sgblack@eecs.umich.edu 597590Sgblack@eecs.umich.edu if (IsOn(ExecTicks)) 607590Sgblack@eecs.umich.edu dumpTicks(outs); 617590Sgblack@eecs.umich.edu 628069SMatt.Horsnell@arm.com outs << thread->getCpuPtr()->name() << " "; 637590Sgblack@eecs.umich.edu 647590Sgblack@eecs.umich.edu if (IsOn(ExecSpeculative)) 657590Sgblack@eecs.umich.edu outs << (misspeculating ? "-" : "+") << " "; 667590Sgblack@eecs.umich.edu 677590Sgblack@eecs.umich.edu if (IsOn(ExecThread)) 687590Sgblack@eecs.umich.edu outs << "T" << thread->threadId() << " : "; 697590Sgblack@eecs.umich.edu 707590Sgblack@eecs.umich.edu std::string sym_str; 717646Sgene.wu@arm.com Addr sym_addr; 727590Sgblack@eecs.umich.edu if (debugSymbolTable 737590Sgblack@eecs.umich.edu && IsOn(ExecSymbol) 747590Sgblack@eecs.umich.edu && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) { 757590Sgblack@eecs.umich.edu if (PC != sym_addr) 767590Sgblack@eecs.umich.edu sym_str += csprintf("+%d", PC - sym_addr); 777590Sgblack@eecs.umich.edu outs << "@" << sym_str; 787590Sgblack@eecs.umich.edu } 797590Sgblack@eecs.umich.edu else { 808069SMatt.Horsnell@arm.com outs << "0x" << hex << PC; 817590Sgblack@eecs.umich.edu } 827590Sgblack@eecs.umich.edu 837590Sgblack@eecs.umich.edu if (inst->isMicroop()) { 847590Sgblack@eecs.umich.edu outs << "." << setw(2) << dec << upc; 857590Sgblack@eecs.umich.edu } else { 867590Sgblack@eecs.umich.edu outs << " "; 877590Sgblack@eecs.umich.edu } 887590Sgblack@eecs.umich.edu 897590Sgblack@eecs.umich.edu outs << " : "; 907590Sgblack@eecs.umich.edu 917590Sgblack@eecs.umich.edu // 927590Sgblack@eecs.umich.edu // Print decoded instruction 937590Sgblack@eecs.umich.edu // 947590Sgblack@eecs.umich.edu 957590Sgblack@eecs.umich.edu outs << setw(26) << left; 967590Sgblack@eecs.umich.edu outs << inst->disassemble(PC, debugSymbolTable); 977590Sgblack@eecs.umich.edu 987590Sgblack@eecs.umich.edu if (ran) { 997590Sgblack@eecs.umich.edu outs << " : "; 1007590Sgblack@eecs.umich.edu 1017590Sgblack@eecs.umich.edu if (IsOn(ExecOpClass)) { 1027590Sgblack@eecs.umich.edu outs << Enums::OpClassStrings[inst->opClass()] << " : "; 1037590Sgblack@eecs.umich.edu } 1047590Sgblack@eecs.umich.edu 1057590Sgblack@eecs.umich.edu if (IsOn(ExecResult) && data_status != DataInvalid) { 1067590Sgblack@eecs.umich.edu ccprintf(outs, " D=%#018x", data.as_int); 1077590Sgblack@eecs.umich.edu } 1087590Sgblack@eecs.umich.edu 1097590Sgblack@eecs.umich.edu if (IsOn(ExecEffAddr) && addr_valid) 1107590Sgblack@eecs.umich.edu outs << " A=0x" << hex << addr; 1117590Sgblack@eecs.umich.edu 1127590Sgblack@eecs.umich.edu if (IsOn(ExecFetchSeq) && fetch_seq_valid) 1138588Sgblack@eecs.umich.edu outs << " FetchSeq=" << dec << fetch_seq; 1148588Sgblack@eecs.umich.edu 1157590Sgblack@eecs.umich.edu if (IsOn(ExecCPSeq) && cp_seq_valid) 1167590Sgblack@eecs.umich.edu outs << " CPSeq=" << dec << cp_seq; 1177590Sgblack@eecs.umich.edu } 1187590Sgblack@eecs.umich.edu 1197590Sgblack@eecs.umich.edu // 1207590Sgblack@eecs.umich.edu // End of line... 1217590Sgblack@eecs.umich.edu // 1227590Sgblack@eecs.umich.edu outs << endl; 1237590Sgblack@eecs.umich.edu} 1247746SAli.Saidi@ARM.com 1257746SAli.Saidi@ARM.comvoid 1267746SAli.Saidi@ARM.comTrace::ExeTracerRecord::dump() 1277746SAli.Saidi@ARM.com{ 1287746SAli.Saidi@ARM.com /* 1297746SAli.Saidi@ARM.com * The behavior this check tries to achieve is that if ExecMacro is on, 1307746SAli.Saidi@ARM.com * the macroop will be printed. If it's on and microops are also on, it's 1317590Sgblack@eecs.umich.edu * printed before the microops start printing to give context. If the 1327590Sgblack@eecs.umich.edu * microops aren't printed, then it's printed only when the final microop 1337590Sgblack@eecs.umich.edu * finishes. Macroops then behave like regular instructions and don't 1347590Sgblack@eecs.umich.edu * complete/print when they fault. 1357746SAli.Saidi@ARM.com */ 1367590Sgblack@eecs.umich.edu if (IsOn(ExecMacro) && staticInst->isMicroop() && 1377590Sgblack@eecs.umich.edu ((IsOn(ExecMicro) && 1387590Sgblack@eecs.umich.edu macroStaticInst && staticInst->isFirstMicroop()) || 1397590Sgblack@eecs.umich.edu (!IsOn(ExecMicro) && 1407590Sgblack@eecs.umich.edu macroStaticInst && staticInst->isLastMicroop()))) { 1417590Sgblack@eecs.umich.edu traceInst(macroStaticInst, false); 1427590Sgblack@eecs.umich.edu } 1437590Sgblack@eecs.umich.edu if (IsOn(ExecMicro) || !staticInst->isMicroop()) { 1447590Sgblack@eecs.umich.edu traceInst(staticInst, true); 1457590Sgblack@eecs.umich.edu } 1467646Sgene.wu@arm.com} 1477646Sgene.wu@arm.com 1487646Sgene.wu@arm.com/* namespace Trace */ } 1497646Sgene.wu@arm.com 1507646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////////// 1517590Sgblack@eecs.umich.edu// 1527590Sgblack@eecs.umich.edu// ExeTracer Simulation Object 1537590Sgblack@eecs.umich.edu// 1547590Sgblack@eecs.umich.eduTrace::ExeTracer * 1558304SAli.Saidi@ARM.comExeTracerParams::create() 1567646Sgene.wu@arm.com{ 1577646Sgene.wu@arm.com return new Trace::ExeTracer(this); 1587646Sgene.wu@arm.com}; 1597646Sgene.wu@arm.com