exetrace.cc revision 3506:99f86646ba5c 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Lisa Hsu
30 *          Nathan Binkert
31 *          Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
40#include "base/loader/symtab.hh"
41#include "cpu/base.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/static_inst.hh"
44#include "sim/param.hh"
45#include "sim/system.hh"
46
47//XXX This is temporary
48#include "arch/isa_specific.hh"
49#include "cpu/m5legion_interface.h"
50
51using namespace std;
52using namespace TheISA;
53
54namespace Trace {
55SharedData *shared_data = NULL;
56}
57
58////////////////////////////////////////////////////////////////////////
59//
60//  Methods for the InstRecord object
61//
62
63
64void
65Trace::InstRecord::dump(ostream &outs)
66{
67    if (flags[PRINT_REG_DELTA])
68    {
69#if THE_ISA == SPARC_ISA
70#if 0
71        //Don't print what happens for each micro-op, just print out
72        //once at the last op, and for regular instructions.
73        if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
74        {
75            static uint64_t regs[32] = {
76                0, 0, 0, 0, 0, 0, 0, 0,
77                0, 0, 0, 0, 0, 0, 0, 0,
78                0, 0, 0, 0, 0, 0, 0, 0,
79                0, 0, 0, 0, 0, 0, 0, 0};
80            static uint64_t ccr = 0;
81            static uint64_t y = 0;
82            static uint64_t floats[32];
83            uint64_t newVal;
84            static const char * prefixes[4] = {"G", "O", "L", "I"};
85
86            char buf[256];
87            sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
88            outs << buf;
89            sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
90            outs << buf;
91            newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
92            if(newVal != ccr)
93            {
94                sprintf(buf, " CCR = 0x%016llx", newVal);
95                outs << buf;
96                ccr = newVal;
97            }
98            newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
99            if(newVal != y)
100            {
101                sprintf(buf, " Y = 0x%016llx", newVal);
102                outs << buf;
103                y = newVal;
104            }
105            for(int y = 0; y < 4; y++)
106            {
107                for(int x = 0; x < 8; x++)
108                {
109                    int index = x + 8 * y;
110                    newVal = thread->readIntReg(index);
111                    if(regs[index] != newVal)
112                    {
113                        sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
114                        outs << buf;
115                        regs[index] = newVal;
116                    }
117                }
118            }
119            for(int y = 0; y < 32; y++)
120            {
121                newVal = thread->readFloatRegBits(2 * y, 64);
122                if(floats[y] != newVal)
123                {
124                    sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal);
125                    outs << buf;
126                    floats[y] = newVal;
127                }
128            }
129            outs << endl;
130        }
131#endif
132#endif
133    }
134    else if (flags[INTEL_FORMAT]) {
135#if FULL_SYSTEM
136        bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
137#else
138        bool is_trace_system = true;
139#endif
140        if (is_trace_system) {
141            ccprintf(outs, "%7d ) ", cycle);
142            outs << "0x" << hex << PC << ":\t";
143            if (staticInst->isLoad()) {
144                outs << "<RD 0x" << hex << addr;
145                outs << ">";
146            } else if (staticInst->isStore()) {
147                outs << "<WR 0x" << hex << addr;
148                outs << ">";
149            }
150            outs << endl;
151        }
152    } else {
153        if (flags[PRINT_CYCLE])
154            ccprintf(outs, "%7d: ", cycle);
155
156        outs << thread->getCpuPtr()->name() << " ";
157
158        if (flags[TRACE_MISSPEC])
159            outs << (misspeculating ? "-" : "+") << " ";
160
161        if (flags[PRINT_THREAD_NUM])
162            outs << "T" << thread->getThreadNum() << " : ";
163
164
165        std::string sym_str;
166        Addr sym_addr;
167        if (debugSymbolTable
168            && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
169            && flags[PC_SYMBOL]) {
170            if (PC != sym_addr)
171                sym_str += csprintf("+%d", PC - sym_addr);
172            outs << "@" << sym_str << " : ";
173        }
174        else {
175            outs << "0x" << hex << PC << " : ";
176        }
177
178        //
179        //  Print decoded instruction
180        //
181
182#if defined(__GNUC__) && (__GNUC__ < 3)
183        // There's a bug in gcc 2.x library that prevents setw()
184        // from working properly on strings
185        string mc(staticInst->disassemble(PC, debugSymbolTable));
186        while (mc.length() < 26)
187            mc += " ";
188        outs << mc;
189#else
190        outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
191#endif
192
193        outs << " : ";
194
195        if (flags[PRINT_OP_CLASS]) {
196            outs << opClassStrings[staticInst->opClass()] << " : ";
197        }
198
199        if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
200            outs << " D=";
201#if 0
202            if (data_status == DataDouble)
203                ccprintf(outs, "%f", data.as_double);
204            else
205                ccprintf(outs, "%#018x", data.as_int);
206#else
207            ccprintf(outs, "%#018x", data.as_int);
208#endif
209        }
210
211        if (flags[PRINT_EFF_ADDR] && addr_valid)
212            outs << " A=0x" << hex << addr;
213
214        if (flags[PRINT_INT_REGS] && regs_valid) {
215            for (int i = 0; i < TheISA::NumIntRegs;)
216                for (int j = i + 1; i <= j; i++)
217                    ccprintf(outs, "r%02d = %#018x%s", i,
218                            iregs->regs.readReg(i),
219                            ((i == j) ? "\n" : "    "));
220            outs << "\n";
221        }
222
223        if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
224            outs << "  FetchSeq=" << dec << fetch_seq;
225
226        if (flags[PRINT_CP_SEQ] && cp_seq_valid)
227            outs << "  CPSeq=" << dec << cp_seq;
228
229        //
230        //  End of line...
231        //
232        outs << endl;
233    }
234    // Compare
235    if (flags[LEGION_LOCKSTEP])
236    {
237        bool compared = false;
238        bool diffPC   = false;
239        bool diffInst = false;
240        bool diffRegs = false;
241
242        while (!compared) {
243            if (shared_data->flags == OWN_M5) {
244                if (shared_data->pc != PC)
245                   diffPC = true;
246                if (shared_data->instruction != staticInst->machInst)
247                    diffInst = true;
248                for (int i = 0; i < TheISA::NumIntRegs; i++) {
249                    if (thread->readIntReg(i) != shared_data->intregs[i])
250                        diffRegs = true;
251                }
252
253                if (diffPC || diffInst || diffRegs ) {
254                    outs << "Differences found between M5 and Legion:";
255                    if (diffPC)
256                        outs << " PC";
257                    if (diffInst)
258                        outs << " Instruction";
259                    if (diffRegs)
260                        outs << " IntRegs";
261                    outs << endl;
262
263                    outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
264                    outs << "Legion PC: " << setw(20) << "0x" << hex <<
265                        shared_data->pc << endl;
266
267
268
269                    outs << "M5 Instruction: " << staticInst->machInst << "("
270                         << staticInst->disassemble(PC, debugSymbolTable)
271                         << ")" << "Legion Instruction: " <<
272                         shared_data->instruction << "("
273                         /*<< legionInst->disassemble(shared_data->pc,
274                                 debugSymbolTable)*/
275                         << ")" << endl;
276
277                    for (int i = 0; i < TheISA::NumIntRegs; i++) {
278                        outs << setw(16) << "0x" << hex << thread->readIntReg(i)
279                             << setw(16) << "0x" << hex << shared_data->intregs[i];
280
281                        if (thread->readIntReg(i) != shared_data->intregs[i])
282                            outs << "<--- Different";
283                        outs << endl;
284                    }
285                }
286
287                compared = true;
288                shared_data->flags = OWN_LEGION;
289            }
290        }
291
292    }
293}
294
295
296vector<bool> Trace::InstRecord::flags(NUM_BITS);
297string Trace::InstRecord::trace_system;
298
299////////////////////////////////////////////////////////////////////////
300//
301// Parameter space for per-cycle execution address tracing options.
302// Derive from ParamContext so we can override checkParams() function.
303//
304class ExecutionTraceParamContext : public ParamContext
305{
306  public:
307    ExecutionTraceParamContext(const string &_iniSection)
308        : ParamContext(_iniSection)
309        {
310        }
311
312    void checkParams();	// defined at bottom of file
313};
314
315ExecutionTraceParamContext exeTraceParams("exetrace");
316
317Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
318                           "capture speculative instructions", true);
319
320Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
321                                  "print cycle number", true);
322Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
323                                  "print op class", true);
324Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
325                                  "print thread number", true);
326Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
327                                  "print effective address", true);
328Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
329                                  "print result data", true);
330Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
331                                  "print all integer regs", false);
332Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
333                                  "print fetch sequence number", false);
334Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
335                                  "print correct-path sequence number", false);
336Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
337                                  "print which registers changed to what", false);
338Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
339                                  "Use symbols for the PC if available", true);
340Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
341                                   "print trace in intel compatible format", false);
342Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
343                                   "Compare sim state to legion state every cycle",
344                                   false);
345Param<string> exe_trace_system(&exeTraceParams, "trace_system",
346                                   "print trace of which system (client or server)",
347                                   "client");
348
349
350//
351// Helper function for ExecutionTraceParamContext::checkParams() just
352// to get us into the InstRecord namespace
353//
354void
355Trace::InstRecord::setParams()
356{
357    flags[TRACE_MISSPEC]     = exe_trace_spec;
358
359    flags[PRINT_CYCLE]       = exe_trace_print_cycle;
360    flags[PRINT_OP_CLASS]    = exe_trace_print_opclass;
361    flags[PRINT_THREAD_NUM]  = exe_trace_print_thread;
362    flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
363    flags[PRINT_EFF_ADDR]    = exe_trace_print_data;
364    flags[PRINT_INT_REGS]    = exe_trace_print_iregs;
365    flags[PRINT_FETCH_SEQ]   = exe_trace_print_fetchseq;
366    flags[PRINT_CP_SEQ]      = exe_trace_print_cp_seq;
367    flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
368    flags[PC_SYMBOL]         = exe_trace_pc_symbol;
369    flags[INTEL_FORMAT]      = exe_trace_intel_format;
370    flags[LEGION_LOCKSTEP]   = exe_trace_legion_lockstep;
371    trace_system	     = exe_trace_system;
372
373    // If were going to be in lockstep with Legion
374    // Setup shared memory, and get otherwise ready
375    if (flags[LEGION_LOCKSTEP]) {
376        int shmfd = shmget(getuid(), sizeof(SharedData), 0777);
377        if (shmfd < 0)
378            fatal("Couldn't get shared memory fd. Is Legion running?");
379
380        shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
381        if (shared_data == (SharedData*)-1)
382            fatal("Couldn't allocate shared memory");
383
384        if (shared_data->flags != OWN_M5)
385            fatal("Shared memory has invalid owner");
386
387        if (shared_data->version != VERSION)
388            fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
389                    shared_data->version);
390
391    }
392}
393
394void
395ExecutionTraceParamContext::checkParams()
396{
397    Trace::InstRecord::setParams();
398}
399
400