exetrace.cc revision 10664:61a0b02aa800
110461SAndreas.Sandberg@ARM.com/* 210461SAndreas.Sandberg@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 310461SAndreas.Sandberg@ARM.com * All rights reserved. 410461SAndreas.Sandberg@ARM.com * 510461SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 610461SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 710461SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 810461SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 910461SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 1010461SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 1110461SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 1210461SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 1310461SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 1410461SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 1510461SAndreas.Sandberg@ARM.com * 1610461SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710461SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810461SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910461SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010461SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110461SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210461SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310461SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410461SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510461SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610461SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710461SAndreas.Sandberg@ARM.com * 2810461SAndreas.Sandberg@ARM.com * Authors: Steve Reinhardt 2910461SAndreas.Sandberg@ARM.com * Lisa Hsu 3010461SAndreas.Sandberg@ARM.com * Nathan Binkert 3110461SAndreas.Sandberg@ARM.com * Steve Raasch 3210461SAndreas.Sandberg@ARM.com */ 3310461SAndreas.Sandberg@ARM.com 3410461SAndreas.Sandberg@ARM.com#include <iomanip> 3510461SAndreas.Sandberg@ARM.com 3610461SAndreas.Sandberg@ARM.com#include "arch/isa_traits.hh" 3710461SAndreas.Sandberg@ARM.com#include "arch/utility.hh" 3810461SAndreas.Sandberg@ARM.com#include "base/loader/symtab.hh" 3910461SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 4010461SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 4110461SAndreas.Sandberg@ARM.com#include "cpu/exetrace.hh" 4210461SAndreas.Sandberg@ARM.com#include "cpu/static_inst.hh" 4310461SAndreas.Sandberg@ARM.com#include "cpu/thread_context.hh" 4410461SAndreas.Sandberg@ARM.com#include "debug/ExecAll.hh" 4510461SAndreas.Sandberg@ARM.com#include "enums/OpClass.hh" 4610461SAndreas.Sandberg@ARM.com 4710609Sandreas.sandberg@arm.comusing namespace std; 4810609Sandreas.sandberg@arm.comusing namespace TheISA; 4910609Sandreas.sandberg@arm.com 5010609Sandreas.sandberg@arm.comnamespace Trace { 5110609Sandreas.sandberg@arm.com 5210609Sandreas.sandberg@arm.comvoid 5310609Sandreas.sandberg@arm.comExeTracerRecord::dumpTicks(ostream &outs) 5410609Sandreas.sandberg@arm.com{ 5510609Sandreas.sandberg@arm.com ccprintf(outs, "%7d: ", when); 5610609Sandreas.sandberg@arm.com} 5710609Sandreas.sandberg@arm.com 5810609Sandreas.sandberg@arm.comvoid 5910609Sandreas.sandberg@arm.comTrace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) 6010461SAndreas.Sandberg@ARM.com{ 6110461SAndreas.Sandberg@ARM.com ostream &outs = Trace::output(); 6210461SAndreas.Sandberg@ARM.com 6310461SAndreas.Sandberg@ARM.com if (!Debug::ExecUser || !Debug::ExecKernel) { 6410461SAndreas.Sandberg@ARM.com bool in_user_mode = TheISA::inUserMode(thread); 6510461SAndreas.Sandberg@ARM.com if (in_user_mode && !Debug::ExecUser) return; 6610461SAndreas.Sandberg@ARM.com if (!in_user_mode && !Debug::ExecKernel) return; 6710461SAndreas.Sandberg@ARM.com } 6810461SAndreas.Sandberg@ARM.com 6910461SAndreas.Sandberg@ARM.com if (Debug::ExecTicks) 7010461SAndreas.Sandberg@ARM.com dumpTicks(outs); 7110461SAndreas.Sandberg@ARM.com 7210461SAndreas.Sandberg@ARM.com outs << thread->getCpuPtr()->name() << " "; 7310461SAndreas.Sandberg@ARM.com 7410461SAndreas.Sandberg@ARM.com if (Debug::ExecAsid) 7510461SAndreas.Sandberg@ARM.com outs << "A" << dec << TheISA::getExecutingAsid(thread) << " "; 76 77 if (Debug::ExecThread) 78 outs << "T" << thread->threadId() << " : "; 79 80 std::string sym_str; 81 Addr sym_addr; 82 Addr cur_pc = pc.instAddr(); 83 if (debugSymbolTable && Debug::ExecSymbol && 84 (!FullSystem || !inUserMode(thread)) && 85 debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { 86 if (cur_pc != sym_addr) 87 sym_str += csprintf("+%d",cur_pc - sym_addr); 88 outs << "@" << sym_str; 89 } else { 90 outs << "0x" << hex << cur_pc; 91 } 92 93 if (inst->isMicroop()) { 94 outs << "." << setw(2) << dec << pc.microPC(); 95 } else { 96 outs << " "; 97 } 98 99 outs << " : "; 100 101 // 102 // Print decoded instruction 103 // 104 105 outs << setw(26) << left; 106 outs << inst->disassemble(cur_pc, debugSymbolTable); 107 108 if (ran) { 109 outs << " : "; 110 111 if (Debug::ExecOpClass) { 112 outs << Enums::OpClassStrings[inst->opClass()] << " : "; 113 } 114 115 if (Debug::ExecResult && !predicate) { 116 outs << "Predicated False"; 117 } 118 119 if (Debug::ExecResult && data_status != DataInvalid) { 120 ccprintf(outs, " D=%#018x", data.as_int); 121 } 122 123 if (Debug::ExecEffAddr && addr_valid) 124 outs << " A=0x" << hex << addr; 125 126 if (Debug::ExecFetchSeq && fetch_seq_valid) 127 outs << " FetchSeq=" << dec << fetch_seq; 128 129 if (Debug::ExecCPSeq && cp_seq_valid) 130 outs << " CPSeq=" << dec << cp_seq; 131 132 if (Debug::ExecFlags) { 133 outs << " flags=("; 134 inst->printFlags(outs, "|"); 135 outs << ")"; 136 } 137 } 138 139 // 140 // End of line... 141 // 142 outs << endl; 143} 144 145void 146Trace::ExeTracerRecord::dump() 147{ 148 /* 149 * The behavior this check tries to achieve is that if ExecMacro is on, 150 * the macroop will be printed. If it's on and microops are also on, it's 151 * printed before the microops start printing to give context. If the 152 * microops aren't printed, then it's printed only when the final microop 153 * finishes. Macroops then behave like regular instructions and don't 154 * complete/print when they fault. 155 */ 156 if (Debug::ExecMacro && staticInst->isMicroop() && 157 ((Debug::ExecMicro && 158 macroStaticInst && staticInst->isFirstMicroop()) || 159 (!Debug::ExecMicro && 160 macroStaticInst && staticInst->isLastMicroop()))) { 161 traceInst(macroStaticInst, false); 162 } 163 if (Debug::ExecMicro || !staticInst->isMicroop()) { 164 traceInst(staticInst, true); 165 } 166} 167 168} // namespace Trace 169 170//////////////////////////////////////////////////////////////////////// 171// 172// ExeTracer Simulation Object 173// 174Trace::ExeTracer * 175ExeTracerParams::create() 176{ 177 return new Trace::ExeTracer(this); 178} 179