exetrace.cc revision 4266
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 394266Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 402973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 413584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4256SN/A#include "base/loader/symtab.hh" 433614Sgblack@eecs.umich.edu#include "config/full_system.hh" 441717SN/A#include "cpu/base.hh" 452518SN/A#include "cpu/exetrace.hh" 4656SN/A#include "cpu/static_inst.hh" 472518SN/A#include "sim/param.hh" 482518SN/A#include "sim/system.hh" 492SN/A 503614Sgblack@eecs.umich.edu#if FULL_SYSTEM 513614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 523614Sgblack@eecs.umich.edu#endif 533614Sgblack@eecs.umich.edu 543065Sgblack@eecs.umich.edu//XXX This is temporary 553065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 563506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 573065Sgblack@eecs.umich.edu 582SN/Ausing namespace std; 592973Sgblack@eecs.umich.eduusing namespace TheISA; 602SN/A 613840Shsul@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 623825Ssaidi@eecs.umich.edustatic int diffcount = 0; 633903Ssaidi@eecs.umich.edustatic bool wasMicro = false; 643840Shsul@eecs.umich.edu#endif 653825Ssaidi@eecs.umich.edu 663506Ssaidi@eecs.umich.edunamespace Trace { 673506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 684054Sbinkertn@umich.edu 694054Sbinkertn@umich.eduvoid 704054Sbinkertn@umich.edusetupSharedData() 714054Sbinkertn@umich.edu{ 724054Sbinkertn@umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 734054Sbinkertn@umich.edu if (shmfd < 0) 744054Sbinkertn@umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 754054Sbinkertn@umich.edu 764054Sbinkertn@umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 774054Sbinkertn@umich.edu if (shared_data == (SharedData*)-1) 784054Sbinkertn@umich.edu fatal("Couldn't allocate shared memory"); 794054Sbinkertn@umich.edu 804054Sbinkertn@umich.edu if (shared_data->flags != OWN_M5) 814054Sbinkertn@umich.edu fatal("Shared memory has invalid owner"); 824054Sbinkertn@umich.edu 834054Sbinkertn@umich.edu if (shared_data->version != VERSION) 844054Sbinkertn@umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 854054Sbinkertn@umich.edu shared_data->version); 864054Sbinkertn@umich.edu 874054Sbinkertn@umich.edu // step legion forward one cycle so we can get register values 884054Sbinkertn@umich.edu shared_data->flags = OWN_LEGION; 893506Ssaidi@eecs.umich.edu} 903506Ssaidi@eecs.umich.edu 912SN/A//////////////////////////////////////////////////////////////////////// 922SN/A// 932SN/A// Methods for the InstRecord object 942SN/A// 952SN/A 963748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 973748Sgblack@eecs.umich.edu 983748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 993748Sgblack@eecs.umich.edu{ 1003748Sgblack@eecs.umich.edu int labelLength = strlen(label); 1013748Sgblack@eecs.umich.edu assert(labelLength <= length); 1023748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 1033748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 1043748Sgblack@eecs.umich.edu char format[64]; 1053748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 1063748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 1073748Sgblack@eecs.umich.edu return buffer; 1083748Sgblack@eecs.umich.edu} 1093748Sgblack@eecs.umich.edu 1103748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 1113748Sgblack@eecs.umich.edu{ 1123748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 1133748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 1143748Sgblack@eecs.umich.edu} 1153748Sgblack@eecs.umich.edu 1163748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 1173748Sgblack@eecs.umich.edu{ 1183748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 1193748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 1203748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 1213748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 1223748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 1233748Sgblack@eecs.umich.edu} 1243748Sgblack@eecs.umich.edu 1253748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1263748Sgblack@eecs.umich.edu{ 1273748Sgblack@eecs.umich.edu char sectionString[70]; 1283748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1293748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1303748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1313748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1323748Sgblack@eecs.umich.edu} 1333748Sgblack@eecs.umich.edu 1343748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1353748Sgblack@eecs.umich.edu{ 1363748Sgblack@eecs.umich.edu char sectionString[70]; 1373748Sgblack@eecs.umich.edu char levelName[70]; 1383748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1393748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1403748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1413748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1423748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1433748Sgblack@eecs.umich.edu} 1443748Sgblack@eecs.umich.edu 1453748Sgblack@eecs.umich.edu#endif 1462SN/A 1472SN/Avoid 1484046Sbinkertn@umich.eduTrace::InstRecord::dump() 1492SN/A{ 1504046Sbinkertn@umich.edu ostream &outs = Trace::output(); 1514046Sbinkertn@umich.edu 1523903Ssaidi@eecs.umich.edu DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); 1534054Sbinkertn@umich.edu if (IsOn(ExecRegDelta)) 1542973Sgblack@eecs.umich.edu { 1553065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1563380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1573380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1583380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1593380Sgblack@eecs.umich.edu { 1603380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1613380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1623380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1633380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1643380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1653380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1663380Sgblack@eecs.umich.edu static uint64_t y = 0; 1673380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1683380Sgblack@eecs.umich.edu uint64_t newVal; 1693380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1703065Sgblack@eecs.umich.edu 1713588Sgblack@eecs.umich.edu outs << hex; 1723588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1733588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1743790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); 1754172Ssaidi@eecs.umich.edu //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR); 1763380Sgblack@eecs.umich.edu if(newVal != ccr) 1773059Sgblack@eecs.umich.edu { 1783588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1793380Sgblack@eecs.umich.edu ccr = newVal; 1803380Sgblack@eecs.umich.edu } 1813790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1); 1824172Ssaidi@eecs.umich.edu //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y); 1833380Sgblack@eecs.umich.edu if(newVal != y) 1843380Sgblack@eecs.umich.edu { 1853588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1863380Sgblack@eecs.umich.edu y = newVal; 1873380Sgblack@eecs.umich.edu } 1883380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1893380Sgblack@eecs.umich.edu { 1903380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1913059Sgblack@eecs.umich.edu { 1923380Sgblack@eecs.umich.edu int index = x + 8 * y; 1933380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1943380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1953380Sgblack@eecs.umich.edu { 1963588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1973380Sgblack@eecs.umich.edu regs[index] = newVal; 1983380Sgblack@eecs.umich.edu } 1993059Sgblack@eecs.umich.edu } 2003059Sgblack@eecs.umich.edu } 2013380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 2023380Sgblack@eecs.umich.edu { 2033380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 2043380Sgblack@eecs.umich.edu if(floats[y] != newVal) 2053380Sgblack@eecs.umich.edu { 2063588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 2073380Sgblack@eecs.umich.edu floats[y] = newVal; 2083380Sgblack@eecs.umich.edu } 2093380Sgblack@eecs.umich.edu } 2103588Sgblack@eecs.umich.edu outs << dec << endl; 2113059Sgblack@eecs.umich.edu } 2123065Sgblack@eecs.umich.edu#endif 2132973Sgblack@eecs.umich.edu } 2144054Sbinkertn@umich.edu else if (IsOn(ExecIntel)) { 2154054Sbinkertn@umich.edu ccprintf(outs, "%7d ) ", when); 2164054Sbinkertn@umich.edu outs << "0x" << hex << PC << ":\t"; 2174054Sbinkertn@umich.edu if (staticInst->isLoad()) { 2184054Sbinkertn@umich.edu ccprintf(outs, "<RD %#x>", addr); 2194054Sbinkertn@umich.edu } else if (staticInst->isStore()) { 2204054Sbinkertn@umich.edu ccprintf(outs, "<WR %#x>", addr); 2211904SN/A } 2224054Sbinkertn@umich.edu outs << endl; 2231904SN/A } else { 2244054Sbinkertn@umich.edu if (IsOn(ExecTicks)) 2254046Sbinkertn@umich.edu ccprintf(outs, "%7d: ", when); 226452SN/A 2273064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2282SN/A 2294054Sbinkertn@umich.edu if (IsOn(ExecSpeculative)) 2301904SN/A outs << (misspeculating ? "-" : "+") << " "; 2312SN/A 2324054Sbinkertn@umich.edu if (IsOn(ExecThread)) 2333064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2342SN/A 2352SN/A 2361904SN/A std::string sym_str; 2371904SN/A Addr sym_addr; 2381904SN/A if (debugSymbolTable 2392299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2404054Sbinkertn@umich.edu && IsOn(ExecSymbol)) { 2411904SN/A if (PC != sym_addr) 2421904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2431904SN/A outs << "@" << sym_str << " : "; 2441904SN/A } 2451904SN/A else { 2461904SN/A outs << "0x" << hex << PC << " : "; 2471904SN/A } 248452SN/A 2491904SN/A // 2501904SN/A // Print decoded instruction 2511904SN/A // 2522SN/A 2532SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2541904SN/A // There's a bug in gcc 2.x library that prevents setw() 2551904SN/A // from working properly on strings 2561904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2571904SN/A while (mc.length() < 26) 2581904SN/A mc += " "; 2591904SN/A outs << mc; 2602SN/A#else 2611904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2622SN/A#endif 2632SN/A 2641904SN/A outs << " : "; 2652SN/A 2664054Sbinkertn@umich.edu if (IsOn(ExecOpClass)) { 2671904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2681904SN/A } 2691904SN/A 2704054Sbinkertn@umich.edu if (IsOn(ExecResult) && data_status != DataInvalid) { 2711904SN/A outs << " D="; 2721904SN/A#if 0 2731904SN/A if (data_status == DataDouble) 2741904SN/A ccprintf(outs, "%f", data.as_double); 2751904SN/A else 2761904SN/A ccprintf(outs, "%#018x", data.as_int); 2771904SN/A#else 2781904SN/A ccprintf(outs, "%#018x", data.as_int); 2791904SN/A#endif 2801904SN/A } 2811904SN/A 2824054Sbinkertn@umich.edu if (IsOn(ExecEffAddr) && addr_valid) 2831904SN/A outs << " A=0x" << hex << addr; 2841904SN/A 2854054Sbinkertn@umich.edu if (IsOn(ExecIntRegs) && regs_valid) { 2862525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2871904SN/A for (int j = i + 1; i <= j; i++) 2882525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2892525SN/A iregs->regs.readReg(i), 2902525SN/A ((i == j) ? "\n" : " ")); 2911904SN/A outs << "\n"; 2921904SN/A } 2931904SN/A 2944054Sbinkertn@umich.edu if (IsOn(ExecFetchSeq) && fetch_seq_valid) 2951904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2961904SN/A 2974054Sbinkertn@umich.edu if (IsOn(ExecCPSeq) && cp_seq_valid) 2981904SN/A outs << " CPSeq=" << dec << cp_seq; 2991967SN/A 3001967SN/A // 3011967SN/A // End of line... 3021967SN/A // 3031967SN/A outs << endl; 3042SN/A } 3053817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 3064266Sgblack@eecs.umich.edu static TheISA::Predecoder predecoder(NULL); 3073506Ssaidi@eecs.umich.edu // Compare 3084054Sbinkertn@umich.edu if (IsOn(ExecLegion)) 3093506Ssaidi@eecs.umich.edu { 3103506Ssaidi@eecs.umich.edu bool compared = false; 3113506Ssaidi@eecs.umich.edu bool diffPC = false; 3123814Ssaidi@eecs.umich.edu bool diffCC = false; 3133506Ssaidi@eecs.umich.edu bool diffInst = false; 3143931Ssaidi@eecs.umich.edu bool diffIntRegs = false; 3153931Ssaidi@eecs.umich.edu bool diffFpRegs = false; 3163748Sgblack@eecs.umich.edu bool diffTpc = false; 3173748Sgblack@eecs.umich.edu bool diffTnpc = false; 3183748Sgblack@eecs.umich.edu bool diffTstate = false; 3193748Sgblack@eecs.umich.edu bool diffTt = false; 3203748Sgblack@eecs.umich.edu bool diffTba = false; 3213748Sgblack@eecs.umich.edu bool diffHpstate = false; 3223748Sgblack@eecs.umich.edu bool diffHtstate = false; 3233748Sgblack@eecs.umich.edu bool diffHtba = false; 3243748Sgblack@eecs.umich.edu bool diffPstate = false; 3253748Sgblack@eecs.umich.edu bool diffY = false; 3264001Ssaidi@eecs.umich.edu bool diffFsr = false; 3273748Sgblack@eecs.umich.edu bool diffCcr = false; 3283748Sgblack@eecs.umich.edu bool diffTl = false; 3293748Sgblack@eecs.umich.edu bool diffGl = false; 3303748Sgblack@eecs.umich.edu bool diffAsi = false; 3313748Sgblack@eecs.umich.edu bool diffPil = false; 3323748Sgblack@eecs.umich.edu bool diffCwp = false; 3333748Sgblack@eecs.umich.edu bool diffCansave = false; 3343748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3353748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3363748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3373880Ssaidi@eecs.umich.edu bool diffTlb = false; 3383603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3393603Ssaidi@eecs.umich.edu 3404054Sbinkertn@umich.edu if (!shared_data) 3414054Sbinkertn@umich.edu setupSharedData(); 3424054Sbinkertn@umich.edu 3433903Ssaidi@eecs.umich.edu // We took a trap on a micro-op... 3443903Ssaidi@eecs.umich.edu if (wasMicro && !staticInst->isMicroOp()) 3453903Ssaidi@eecs.umich.edu { 3464046Sbinkertn@umich.edu // let's skip comparing this tick 3473903Ssaidi@eecs.umich.edu while (!compared) 3483903Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3493903Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3503903Ssaidi@eecs.umich.edu compared = true; 3513903Ssaidi@eecs.umich.edu } 3523903Ssaidi@eecs.umich.edu compared = false; 3533903Ssaidi@eecs.umich.edu wasMicro = false; 3543903Ssaidi@eecs.umich.edu } 3553903Ssaidi@eecs.umich.edu 3563903Ssaidi@eecs.umich.edu if (staticInst->isLastMicroOp()) 3573903Ssaidi@eecs.umich.edu wasMicro = false; 3583903Ssaidi@eecs.umich.edu else if (staticInst->isMicroOp()) 3593903Ssaidi@eecs.umich.edu wasMicro = true; 3603903Ssaidi@eecs.umich.edu 3613506Ssaidi@eecs.umich.edu 3623584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3633584Ssaidi@eecs.umich.edu while (!compared) { 3643584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3653748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3663928Ssaidi@eecs.umich.edu if (bits(shared_data->pstate,3,3)) { 3673928Ssaidi@eecs.umich.edu m5Pc &= mask(32); 3683928Ssaidi@eecs.umich.edu } 3693748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3703603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3713584Ssaidi@eecs.umich.edu diffPC = true; 3723814Ssaidi@eecs.umich.edu 3733814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 3743814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 3753814Ssaidi@eecs.umich.edu diffCC = true; 3763814Ssaidi@eecs.umich.edu 3773743Sgblack@eecs.umich.edu if (shared_data->instruction != 3783743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3793584Ssaidi@eecs.umich.edu diffInst = true; 3803743Sgblack@eecs.umich.edu } 3813989Ssaidi@eecs.umich.edu // assume we have %g0 working correctly 3823989Ssaidi@eecs.umich.edu for (int i = 1; i < TheISA::NumIntArchRegs; i++) { 3833603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3843931Ssaidi@eecs.umich.edu diffIntRegs = true; 3853603Ssaidi@eecs.umich.edu } 3863584Ssaidi@eecs.umich.edu } 3873931Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { 3883945Ssaidi@eecs.umich.edu if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { 3893931Ssaidi@eecs.umich.edu diffFpRegs = true; 3903931Ssaidi@eecs.umich.edu } 3913931Ssaidi@eecs.umich.edu } 3924172Ssaidi@eecs.umich.edu uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL); 3933748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3943748Sgblack@eecs.umich.edu diffTl = true; 3953748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3964172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, i); 3974172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TPC) != 3983815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 3993748Sgblack@eecs.umich.edu diffTpc = true; 4004172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TNPC) != 4013815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 4023748Sgblack@eecs.umich.edu diffTnpc = true; 4034172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TSTATE) != 4043815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 4053748Sgblack@eecs.umich.edu diffTstate = true; 4064172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TT) != 4073815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 4083748Sgblack@eecs.umich.edu diffTt = true; 4094172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) != 4103815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 4113748Sgblack@eecs.umich.edu diffHtstate = true; 4123748Sgblack@eecs.umich.edu } 4134172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, oldTl); 4143584Ssaidi@eecs.umich.edu 4154172Ssaidi@eecs.umich.edu if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA)) 4163748Sgblack@eecs.umich.edu diffTba = true; 4173748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 4183748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 4193748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 4203748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 4213748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 4223748Sgblack@eecs.umich.edu //anyway. 4234172Ssaidi@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE)) 4243748Sgblack@eecs.umich.edu diffHpstate = true; 4254172Ssaidi@eecs.umich.edu if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA)) 4263748Sgblack@eecs.umich.edu diffHtba = true; 4274172Ssaidi@eecs.umich.edu if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE)) 4283748Sgblack@eecs.umich.edu diffPstate = true; 4294172Ssaidi@eecs.umich.edu //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y)) 4303790Sgblack@eecs.umich.edu if(shared_data->y != 4313790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1)) 4323748Sgblack@eecs.umich.edu diffY = true; 4334172Ssaidi@eecs.umich.edu if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) { 4344001Ssaidi@eecs.umich.edu diffFsr = true; 4354011Ssaidi@eecs.umich.edu if (mbits(shared_data->fsr, 63,10) == 4364172Ssaidi@eecs.umich.edu mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) { 4374172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr); 4384011Ssaidi@eecs.umich.edu diffFsr = false; 4394011Ssaidi@eecs.umich.edu } 4404011Ssaidi@eecs.umich.edu } 4414172Ssaidi@eecs.umich.edu //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR)) 4423790Sgblack@eecs.umich.edu if(shared_data->ccr != 4433790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2)) 4443748Sgblack@eecs.umich.edu diffCcr = true; 4454172Ssaidi@eecs.umich.edu if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL)) 4463748Sgblack@eecs.umich.edu diffGl = true; 4474172Ssaidi@eecs.umich.edu if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI)) 4483748Sgblack@eecs.umich.edu diffAsi = true; 4494172Ssaidi@eecs.umich.edu if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL)) 4503748Sgblack@eecs.umich.edu diffPil = true; 4514172Ssaidi@eecs.umich.edu if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP)) 4523748Sgblack@eecs.umich.edu diffCwp = true; 4534172Ssaidi@eecs.umich.edu //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE)) 4543790Sgblack@eecs.umich.edu if(shared_data->cansave != 4553790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3)) 4563748Sgblack@eecs.umich.edu diffCansave = true; 4573790Sgblack@eecs.umich.edu //if(shared_data->canrestore != 4584172Ssaidi@eecs.umich.edu // thread->readMiscRegNoEffect(MISCREG_CANRESTORE)) 4593748Sgblack@eecs.umich.edu if(shared_data->canrestore != 4603989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4)) 4613748Sgblack@eecs.umich.edu diffCanrestore = true; 4624172Ssaidi@eecs.umich.edu //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN)) 4633790Sgblack@eecs.umich.edu if(shared_data->otherwin != 4643989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6)) 4653748Sgblack@eecs.umich.edu diffOtherwin = true; 4664172Ssaidi@eecs.umich.edu //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN)) 4673790Sgblack@eecs.umich.edu if(shared_data->cleanwin != 4683989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5)) 4693748Sgblack@eecs.umich.edu diffCleanwin = true; 4703748Sgblack@eecs.umich.edu 4713880Ssaidi@eecs.umich.edu for (int i = 0; i < 64; i++) { 4723880Ssaidi@eecs.umich.edu if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) 4733880Ssaidi@eecs.umich.edu diffTlb = true; 4743880Ssaidi@eecs.umich.edu if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) 4753880Ssaidi@eecs.umich.edu diffTlb = true; 4763880Ssaidi@eecs.umich.edu } 4773880Ssaidi@eecs.umich.edu 4784008Ssaidi@eecs.umich.edu if (diffPC || diffCC || diffInst || diffIntRegs || 4793931Ssaidi@eecs.umich.edu diffFpRegs || diffTpc || diffTnpc || diffTstate || 4803931Ssaidi@eecs.umich.edu diffTt || diffHpstate || diffHtstate || diffHtba || 4814001Ssaidi@eecs.umich.edu diffPstate || diffY || diffCcr || diffTl || diffFsr || 4824001Ssaidi@eecs.umich.edu diffGl || diffAsi || diffPil || diffCwp || diffCansave || 4833931Ssaidi@eecs.umich.edu diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) 4844008Ssaidi@eecs.umich.edu { 4853863Ssaidi@eecs.umich.edu 4863584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 4873584Ssaidi@eecs.umich.edu if (diffPC) 4883584Ssaidi@eecs.umich.edu outs << " [PC]"; 4893814Ssaidi@eecs.umich.edu if (diffCC) 4903814Ssaidi@eecs.umich.edu outs << " [CC]"; 4913584Ssaidi@eecs.umich.edu if (diffInst) 4923584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 4933931Ssaidi@eecs.umich.edu if (diffIntRegs) 4943584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4953931Ssaidi@eecs.umich.edu if (diffFpRegs) 4963931Ssaidi@eecs.umich.edu outs << " [FpRegs]"; 4973748Sgblack@eecs.umich.edu if (diffTpc) 4983748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4993748Sgblack@eecs.umich.edu if (diffTnpc) 5003748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 5013748Sgblack@eecs.umich.edu if (diffTstate) 5023748Sgblack@eecs.umich.edu outs << " [Tstate]"; 5033748Sgblack@eecs.umich.edu if (diffTt) 5043748Sgblack@eecs.umich.edu outs << " [Tt]"; 5053748Sgblack@eecs.umich.edu if (diffHpstate) 5063748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 5073748Sgblack@eecs.umich.edu if (diffHtstate) 5083748Sgblack@eecs.umich.edu outs << " [Htstate]"; 5093748Sgblack@eecs.umich.edu if (diffHtba) 5103748Sgblack@eecs.umich.edu outs << " [Htba]"; 5113748Sgblack@eecs.umich.edu if (diffPstate) 5123748Sgblack@eecs.umich.edu outs << " [Pstate]"; 5133748Sgblack@eecs.umich.edu if (diffY) 5143748Sgblack@eecs.umich.edu outs << " [Y]"; 5154001Ssaidi@eecs.umich.edu if (diffFsr) 5164001Ssaidi@eecs.umich.edu outs << " [FSR]"; 5173748Sgblack@eecs.umich.edu if (diffCcr) 5183748Sgblack@eecs.umich.edu outs << " [Ccr]"; 5193748Sgblack@eecs.umich.edu if (diffTl) 5203748Sgblack@eecs.umich.edu outs << " [Tl]"; 5213748Sgblack@eecs.umich.edu if (diffGl) 5223748Sgblack@eecs.umich.edu outs << " [Gl]"; 5233748Sgblack@eecs.umich.edu if (diffAsi) 5243748Sgblack@eecs.umich.edu outs << " [Asi]"; 5253748Sgblack@eecs.umich.edu if (diffPil) 5263748Sgblack@eecs.umich.edu outs << " [Pil]"; 5273748Sgblack@eecs.umich.edu if (diffCwp) 5283748Sgblack@eecs.umich.edu outs << " [Cwp]"; 5293748Sgblack@eecs.umich.edu if (diffCansave) 5303748Sgblack@eecs.umich.edu outs << " [Cansave]"; 5313748Sgblack@eecs.umich.edu if (diffCanrestore) 5323748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 5333748Sgblack@eecs.umich.edu if (diffOtherwin) 5343748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 5353748Sgblack@eecs.umich.edu if (diffCleanwin) 5363748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 5373880Ssaidi@eecs.umich.edu if (diffTlb) 5383880Ssaidi@eecs.umich.edu outs << " [Tlb]"; 5393603Ssaidi@eecs.umich.edu outs << endl << endl; 5403584Ssaidi@eecs.umich.edu 5413603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5423584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 5433603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 5443584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5453584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 5463603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 5473584Ssaidi@eecs.umich.edu 5483814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5493814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 5503814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 5513814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5523814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 5533814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 5543814Ssaidi@eecs.umich.edu 5553584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5563584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 5573584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 5583603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 5593584Ssaidi@eecs.umich.edu << endl; 5603584Ssaidi@eecs.umich.edu 5614266Sgblack@eecs.umich.edu predecoder.setTC(thread); 5624266Sgblack@eecs.umich.edu predecoder.moreBytes(m5Pc, 0, shared_data->instruction); 5634266Sgblack@eecs.umich.edu 5644266Sgblack@eecs.umich.edu assert(predecoder.extMachInstRead()); 5654266Sgblack@eecs.umich.edu 5663748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 5674266Sgblack@eecs.umich.edu StaticInst::decode(predecoder.getExtMachInst()); 5683584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5693584Ssaidi@eecs.umich.edu << " Legion Inst: " 5703584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 5713584Ssaidi@eecs.umich.edu << shared_data->instruction 5723603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 5733748Sgblack@eecs.umich.edu << endl << endl; 5743584Ssaidi@eecs.umich.edu 5753748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 5763748Sgblack@eecs.umich.edu printColumnLabels(outs); 5773748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 5784172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HPSTATE), 5793748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 5803748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 5814172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HTBA), 5823748Sgblack@eecs.umich.edu shared_data->htba); 5833748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 5844172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_PSTATE), 5853748Sgblack@eecs.umich.edu shared_data->pstate); 5863748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 5874172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_Y), 5883989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1), 5893748Sgblack@eecs.umich.edu shared_data->y); 5904001Ssaidi@eecs.umich.edu printRegPair(outs, "FSR", 5914172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_FSR), 5924001Ssaidi@eecs.umich.edu shared_data->fsr); 5933748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 5944172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CCR), 5953989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2), 5963748Sgblack@eecs.umich.edu shared_data->ccr); 5973748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 5984172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TL), 5993748Sgblack@eecs.umich.edu shared_data->tl); 6003748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 6014172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_GL), 6023748Sgblack@eecs.umich.edu shared_data->gl); 6033748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 6044172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_ASI), 6053748Sgblack@eecs.umich.edu shared_data->asi); 6063748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 6074172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_PIL), 6083748Sgblack@eecs.umich.edu shared_data->pil); 6093748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 6104172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_CWP), 6113748Sgblack@eecs.umich.edu shared_data->cwp); 6123748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 6134172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CANSAVE), 6143790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3), 6153748Sgblack@eecs.umich.edu shared_data->cansave); 6163748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 6174172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CANRESTORE), 6183790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4), 6193748Sgblack@eecs.umich.edu shared_data->canrestore); 6203748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 6214172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_OTHERWIN), 6223989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6), 6233748Sgblack@eecs.umich.edu shared_data->otherwin); 6243748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 6254172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CLEANWIN), 6263989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5), 6273748Sgblack@eecs.umich.edu shared_data->cleanwin); 6283748Sgblack@eecs.umich.edu outs << endl; 6293748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 6303748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 6313748Sgblack@eecs.umich.edu printColumnLabels(outs); 6324172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, i); 6333748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 6344172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TPC), 6353815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 6363748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 6374172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TNPC), 6383815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 6393748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 6404172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TSTATE), 6413815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 6423748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 6434172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TT), 6443815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 6453748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 6464172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HTSTATE), 6473815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 6483748Sgblack@eecs.umich.edu } 6494172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, oldTl); 6503584Ssaidi@eecs.umich.edu outs << endl; 6513584Ssaidi@eecs.umich.edu 6523748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 6533584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 6543931Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) { 6553931Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) { 6563748Sgblack@eecs.umich.edu char label[8]; 6573748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 6583748Sgblack@eecs.umich.edu printRegPair(outs, label, 6593748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 6603748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 6613931Ssaidi@eecs.umich.edu } 6623931Ssaidi@eecs.umich.edu } 6633931Ssaidi@eecs.umich.edu if (diffFpRegs) { 6643931Ssaidi@eecs.umich.edu for (int x = 0; x < 32; x++) { 6653931Ssaidi@eecs.umich.edu char label[8]; 6663931Ssaidi@eecs.umich.edu sprintf(label, "%%f%d", x); 6673931Ssaidi@eecs.umich.edu printRegPair(outs, label, 6684008Ssaidi@eecs.umich.edu thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), 6693931Ssaidi@eecs.umich.edu shared_data->fpregs[x]); 6703584Ssaidi@eecs.umich.edu } 6713584Ssaidi@eecs.umich.edu } 6723903Ssaidi@eecs.umich.edu if (diffTlb) { 6733903Ssaidi@eecs.umich.edu printColumnLabels(outs); 6743903Ssaidi@eecs.umich.edu char label[8]; 6753903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6763903Ssaidi@eecs.umich.edu if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6773903Ssaidi@eecs.umich.edu thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6783903Ssaidi@eecs.umich.edu sprintf(label, "I-TLB:%02d", x); 6793903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getITBPtr()->TteRead(x), 6803903Ssaidi@eecs.umich.edu shared_data->itb[x]); 6813903Ssaidi@eecs.umich.edu } 6823880Ssaidi@eecs.umich.edu } 6833903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6843903Ssaidi@eecs.umich.edu if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6853903Ssaidi@eecs.umich.edu thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6863903Ssaidi@eecs.umich.edu sprintf(label, "D-TLB:%02d", x); 6873903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), 6883903Ssaidi@eecs.umich.edu shared_data->dtb[x]); 6893903Ssaidi@eecs.umich.edu } 6903903Ssaidi@eecs.umich.edu } 6913903Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 6923903Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 6933880Ssaidi@eecs.umich.edu } 6943826Ssaidi@eecs.umich.edu 6953825Ssaidi@eecs.umich.edu diffcount++; 6964011Ssaidi@eecs.umich.edu if (diffcount > 3) 6973825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 6983892Ssaidi@eecs.umich.edu } else 6993892Ssaidi@eecs.umich.edu diffcount = 0; 7003584Ssaidi@eecs.umich.edu 7013584Ssaidi@eecs.umich.edu compared = true; 7023584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 7033506Ssaidi@eecs.umich.edu } 7043584Ssaidi@eecs.umich.edu } // while 7053584Ssaidi@eecs.umich.edu } // if not microop 7063506Ssaidi@eecs.umich.edu } 7073584Ssaidi@eecs.umich.edu#endif 7082SN/A} 7092SN/A 7104054Sbinkertn@umich.edu/* namespace Trace */ } 711