exetrace.cc revision 4011
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603840Shsul@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 613825Ssaidi@eecs.umich.edustatic int diffcount = 0; 623903Ssaidi@eecs.umich.edustatic bool wasMicro = false; 633840Shsul@eecs.umich.edu#endif 643825Ssaidi@eecs.umich.edu 653506Ssaidi@eecs.umich.edunamespace Trace { 663506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 673506Ssaidi@eecs.umich.edu} 683506Ssaidi@eecs.umich.edu 692SN/A//////////////////////////////////////////////////////////////////////// 702SN/A// 712SN/A// Methods for the InstRecord object 722SN/A// 732SN/A 743748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 753748Sgblack@eecs.umich.edu 763748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 773748Sgblack@eecs.umich.edu{ 783748Sgblack@eecs.umich.edu int labelLength = strlen(label); 793748Sgblack@eecs.umich.edu assert(labelLength <= length); 803748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 813748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 823748Sgblack@eecs.umich.edu char format[64]; 833748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 843748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 853748Sgblack@eecs.umich.edu return buffer; 863748Sgblack@eecs.umich.edu} 873748Sgblack@eecs.umich.edu 883748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 893748Sgblack@eecs.umich.edu{ 903748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 913748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 923748Sgblack@eecs.umich.edu} 933748Sgblack@eecs.umich.edu 943748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 953748Sgblack@eecs.umich.edu{ 963748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 973748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 983748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 993748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 1003748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 1013748Sgblack@eecs.umich.edu} 1023748Sgblack@eecs.umich.edu 1033748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1043748Sgblack@eecs.umich.edu{ 1053748Sgblack@eecs.umich.edu char sectionString[70]; 1063748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1073748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1083748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1093748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1103748Sgblack@eecs.umich.edu} 1113748Sgblack@eecs.umich.edu 1123748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1133748Sgblack@eecs.umich.edu{ 1143748Sgblack@eecs.umich.edu char sectionString[70]; 1153748Sgblack@eecs.umich.edu char levelName[70]; 1163748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1173748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1183748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1193748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1203748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1213748Sgblack@eecs.umich.edu} 1223748Sgblack@eecs.umich.edu 1233748Sgblack@eecs.umich.edu#endif 1242SN/A 1252SN/Avoid 1262SN/ATrace::InstRecord::dump(ostream &outs) 1272SN/A{ 1283903Ssaidi@eecs.umich.edu DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); 1292973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 1302973Sgblack@eecs.umich.edu { 1313065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1323380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1333380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1343380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1353380Sgblack@eecs.umich.edu { 1363380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1373380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1383380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1393380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1403380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1413380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1423380Sgblack@eecs.umich.edu static uint64_t y = 0; 1433380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1443380Sgblack@eecs.umich.edu uint64_t newVal; 1453380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1463065Sgblack@eecs.umich.edu 1473588Sgblack@eecs.umich.edu outs << hex; 1483588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1493588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1503790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); 1513790Sgblack@eecs.umich.edu //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 1523380Sgblack@eecs.umich.edu if(newVal != ccr) 1533059Sgblack@eecs.umich.edu { 1543588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1553380Sgblack@eecs.umich.edu ccr = newVal; 1563380Sgblack@eecs.umich.edu } 1573790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1); 1583790Sgblack@eecs.umich.edu //newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1593380Sgblack@eecs.umich.edu if(newVal != y) 1603380Sgblack@eecs.umich.edu { 1613588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1623380Sgblack@eecs.umich.edu y = newVal; 1633380Sgblack@eecs.umich.edu } 1643380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1653380Sgblack@eecs.umich.edu { 1663380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1673059Sgblack@eecs.umich.edu { 1683380Sgblack@eecs.umich.edu int index = x + 8 * y; 1693380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1703380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1713380Sgblack@eecs.umich.edu { 1723588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1733380Sgblack@eecs.umich.edu regs[index] = newVal; 1743380Sgblack@eecs.umich.edu } 1753059Sgblack@eecs.umich.edu } 1763059Sgblack@eecs.umich.edu } 1773380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1783380Sgblack@eecs.umich.edu { 1793380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1803380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1813380Sgblack@eecs.umich.edu { 1823588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1833380Sgblack@eecs.umich.edu floats[y] = newVal; 1843380Sgblack@eecs.umich.edu } 1853380Sgblack@eecs.umich.edu } 1863588Sgblack@eecs.umich.edu outs << dec << endl; 1873059Sgblack@eecs.umich.edu } 1883065Sgblack@eecs.umich.edu#endif 1892973Sgblack@eecs.umich.edu } 1902973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1911968SN/A#if FULL_SYSTEM 1923064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1931968SN/A#else 1941968SN/A bool is_trace_system = true; 1951968SN/A#endif 1961968SN/A if (is_trace_system) { 1971967SN/A ccprintf(outs, "%7d ) ", cycle); 1981967SN/A outs << "0x" << hex << PC << ":\t"; 1991967SN/A if (staticInst->isLoad()) { 2001967SN/A outs << "<RD 0x" << hex << addr; 2011967SN/A outs << ">"; 2021967SN/A } else if (staticInst->isStore()) { 2031967SN/A outs << "<WR 0x" << hex << addr; 2041967SN/A outs << ">"; 2051967SN/A } 2061967SN/A outs << endl; 2071904SN/A } 2081904SN/A } else { 2091904SN/A if (flags[PRINT_CYCLE]) 2101904SN/A ccprintf(outs, "%7d: ", cycle); 211452SN/A 2123064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2132SN/A 2141904SN/A if (flags[TRACE_MISSPEC]) 2151904SN/A outs << (misspeculating ? "-" : "+") << " "; 2162SN/A 2171904SN/A if (flags[PRINT_THREAD_NUM]) 2183064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2192SN/A 2202SN/A 2211904SN/A std::string sym_str; 2221904SN/A Addr sym_addr; 2231904SN/A if (debugSymbolTable 2242299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2252299SN/A && flags[PC_SYMBOL]) { 2261904SN/A if (PC != sym_addr) 2271904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2281904SN/A outs << "@" << sym_str << " : "; 2291904SN/A } 2301904SN/A else { 2311904SN/A outs << "0x" << hex << PC << " : "; 2321904SN/A } 233452SN/A 2341904SN/A // 2351904SN/A // Print decoded instruction 2361904SN/A // 2372SN/A 2382SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2391904SN/A // There's a bug in gcc 2.x library that prevents setw() 2401904SN/A // from working properly on strings 2411904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2421904SN/A while (mc.length() < 26) 2431904SN/A mc += " "; 2441904SN/A outs << mc; 2452SN/A#else 2461904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2472SN/A#endif 2482SN/A 2491904SN/A outs << " : "; 2502SN/A 2511904SN/A if (flags[PRINT_OP_CLASS]) { 2521904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2531904SN/A } 2541904SN/A 2551904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2561904SN/A outs << " D="; 2571904SN/A#if 0 2581904SN/A if (data_status == DataDouble) 2591904SN/A ccprintf(outs, "%f", data.as_double); 2601904SN/A else 2611904SN/A ccprintf(outs, "%#018x", data.as_int); 2621904SN/A#else 2631904SN/A ccprintf(outs, "%#018x", data.as_int); 2641904SN/A#endif 2651904SN/A } 2661904SN/A 2671904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2681904SN/A outs << " A=0x" << hex << addr; 2691904SN/A 2701904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2712525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2721904SN/A for (int j = i + 1; i <= j; i++) 2732525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2742525SN/A iregs->regs.readReg(i), 2752525SN/A ((i == j) ? "\n" : " ")); 2761904SN/A outs << "\n"; 2771904SN/A } 2781904SN/A 2791904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2801904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2811904SN/A 2821904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2831904SN/A outs << " CPSeq=" << dec << cp_seq; 2841967SN/A 2851967SN/A // 2861967SN/A // End of line... 2871967SN/A // 2881967SN/A outs << endl; 2892SN/A } 2903817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 2913506Ssaidi@eecs.umich.edu // Compare 2923506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2933506Ssaidi@eecs.umich.edu { 2943506Ssaidi@eecs.umich.edu bool compared = false; 2953506Ssaidi@eecs.umich.edu bool diffPC = false; 2963814Ssaidi@eecs.umich.edu bool diffCC = false; 2973506Ssaidi@eecs.umich.edu bool diffInst = false; 2983931Ssaidi@eecs.umich.edu bool diffIntRegs = false; 2993931Ssaidi@eecs.umich.edu bool diffFpRegs = false; 3003748Sgblack@eecs.umich.edu bool diffTpc = false; 3013748Sgblack@eecs.umich.edu bool diffTnpc = false; 3023748Sgblack@eecs.umich.edu bool diffTstate = false; 3033748Sgblack@eecs.umich.edu bool diffTt = false; 3043748Sgblack@eecs.umich.edu bool diffTba = false; 3053748Sgblack@eecs.umich.edu bool diffHpstate = false; 3063748Sgblack@eecs.umich.edu bool diffHtstate = false; 3073748Sgblack@eecs.umich.edu bool diffHtba = false; 3083748Sgblack@eecs.umich.edu bool diffPstate = false; 3093748Sgblack@eecs.umich.edu bool diffY = false; 3104001Ssaidi@eecs.umich.edu bool diffFsr = false; 3113748Sgblack@eecs.umich.edu bool diffCcr = false; 3123748Sgblack@eecs.umich.edu bool diffTl = false; 3133748Sgblack@eecs.umich.edu bool diffGl = false; 3143748Sgblack@eecs.umich.edu bool diffAsi = false; 3153748Sgblack@eecs.umich.edu bool diffPil = false; 3163748Sgblack@eecs.umich.edu bool diffCwp = false; 3173748Sgblack@eecs.umich.edu bool diffCansave = false; 3183748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3193748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3203748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3213880Ssaidi@eecs.umich.edu bool diffTlb = false; 3223603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3233603Ssaidi@eecs.umich.edu 3243903Ssaidi@eecs.umich.edu // We took a trap on a micro-op... 3253903Ssaidi@eecs.umich.edu if (wasMicro && !staticInst->isMicroOp()) 3263903Ssaidi@eecs.umich.edu { 3273903Ssaidi@eecs.umich.edu // let's skip comparing this cycle 3283903Ssaidi@eecs.umich.edu while (!compared) 3293903Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3303903Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3313903Ssaidi@eecs.umich.edu compared = true; 3323903Ssaidi@eecs.umich.edu } 3333903Ssaidi@eecs.umich.edu compared = false; 3343903Ssaidi@eecs.umich.edu wasMicro = false; 3353903Ssaidi@eecs.umich.edu } 3363903Ssaidi@eecs.umich.edu 3373903Ssaidi@eecs.umich.edu if (staticInst->isLastMicroOp()) 3383903Ssaidi@eecs.umich.edu wasMicro = false; 3393903Ssaidi@eecs.umich.edu else if (staticInst->isMicroOp()) 3403903Ssaidi@eecs.umich.edu wasMicro = true; 3413903Ssaidi@eecs.umich.edu 3423506Ssaidi@eecs.umich.edu 3433584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3443584Ssaidi@eecs.umich.edu while (!compared) { 3453584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3463748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3473928Ssaidi@eecs.umich.edu if (bits(shared_data->pstate,3,3)) { 3483928Ssaidi@eecs.umich.edu m5Pc &= mask(32); 3493928Ssaidi@eecs.umich.edu } 3503748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3513603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3523584Ssaidi@eecs.umich.edu diffPC = true; 3533814Ssaidi@eecs.umich.edu 3543814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 3553814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 3563814Ssaidi@eecs.umich.edu diffCC = true; 3573814Ssaidi@eecs.umich.edu 3583743Sgblack@eecs.umich.edu if (shared_data->instruction != 3593743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3603584Ssaidi@eecs.umich.edu diffInst = true; 3613743Sgblack@eecs.umich.edu } 3623989Ssaidi@eecs.umich.edu // assume we have %g0 working correctly 3633989Ssaidi@eecs.umich.edu for (int i = 1; i < TheISA::NumIntArchRegs; i++) { 3643603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3653931Ssaidi@eecs.umich.edu diffIntRegs = true; 3663603Ssaidi@eecs.umich.edu } 3673584Ssaidi@eecs.umich.edu } 3683931Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { 3693945Ssaidi@eecs.umich.edu if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { 3703931Ssaidi@eecs.umich.edu diffFpRegs = true; 3713931Ssaidi@eecs.umich.edu } 3723931Ssaidi@eecs.umich.edu } 3733931Ssaidi@eecs.umich.edu uint64_t oldTl = thread->readMiscReg(MISCREG_TL); 3743748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3753748Sgblack@eecs.umich.edu diffTl = true; 3763748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3773748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 3783748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TPC) != 3793815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 3803748Sgblack@eecs.umich.edu diffTpc = true; 3813748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TNPC) != 3823815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 3833748Sgblack@eecs.umich.edu diffTnpc = true; 3843748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TSTATE) != 3853815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 3863748Sgblack@eecs.umich.edu diffTstate = true; 3873748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TT) != 3883815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 3893748Sgblack@eecs.umich.edu diffTt = true; 3903748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_HTSTATE) != 3913815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 3923748Sgblack@eecs.umich.edu diffHtstate = true; 3933748Sgblack@eecs.umich.edu } 3943748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 3953584Ssaidi@eecs.umich.edu 3963748Sgblack@eecs.umich.edu if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) 3973748Sgblack@eecs.umich.edu diffTba = true; 3983748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 3993748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 4003748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 4013748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 4023748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 4033748Sgblack@eecs.umich.edu //anyway. 4043748Sgblack@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) 4053748Sgblack@eecs.umich.edu diffHpstate = true; 4063748Sgblack@eecs.umich.edu if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) 4073748Sgblack@eecs.umich.edu diffHtba = true; 4083748Sgblack@eecs.umich.edu if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) 4093748Sgblack@eecs.umich.edu diffPstate = true; 4103790Sgblack@eecs.umich.edu //if(shared_data->y != thread->readMiscReg(MISCREG_Y)) 4113790Sgblack@eecs.umich.edu if(shared_data->y != 4123790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1)) 4133748Sgblack@eecs.umich.edu diffY = true; 4144011Ssaidi@eecs.umich.edu if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) { 4154001Ssaidi@eecs.umich.edu diffFsr = true; 4164011Ssaidi@eecs.umich.edu if (mbits(shared_data->fsr, 63,10) == 4174011Ssaidi@eecs.umich.edu mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) { 4184011Ssaidi@eecs.umich.edu thread->setMiscReg(MISCREG_FSR, shared_data->fsr); 4194011Ssaidi@eecs.umich.edu diffFsr = false; 4204011Ssaidi@eecs.umich.edu } 4214011Ssaidi@eecs.umich.edu } 4223790Sgblack@eecs.umich.edu //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) 4233790Sgblack@eecs.umich.edu if(shared_data->ccr != 4243790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2)) 4253748Sgblack@eecs.umich.edu diffCcr = true; 4263748Sgblack@eecs.umich.edu if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) 4273748Sgblack@eecs.umich.edu diffGl = true; 4283748Sgblack@eecs.umich.edu if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) 4293748Sgblack@eecs.umich.edu diffAsi = true; 4303748Sgblack@eecs.umich.edu if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) 4313748Sgblack@eecs.umich.edu diffPil = true; 4323748Sgblack@eecs.umich.edu if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) 4333748Sgblack@eecs.umich.edu diffCwp = true; 4343790Sgblack@eecs.umich.edu //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) 4353790Sgblack@eecs.umich.edu if(shared_data->cansave != 4363790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3)) 4373748Sgblack@eecs.umich.edu diffCansave = true; 4383790Sgblack@eecs.umich.edu //if(shared_data->canrestore != 4393790Sgblack@eecs.umich.edu // thread->readMiscReg(MISCREG_CANRESTORE)) 4403748Sgblack@eecs.umich.edu if(shared_data->canrestore != 4413989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4)) 4423748Sgblack@eecs.umich.edu diffCanrestore = true; 4433790Sgblack@eecs.umich.edu //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) 4443790Sgblack@eecs.umich.edu if(shared_data->otherwin != 4453989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6)) 4463748Sgblack@eecs.umich.edu diffOtherwin = true; 4473790Sgblack@eecs.umich.edu //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) 4483790Sgblack@eecs.umich.edu if(shared_data->cleanwin != 4493989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5)) 4503748Sgblack@eecs.umich.edu diffCleanwin = true; 4513748Sgblack@eecs.umich.edu 4523880Ssaidi@eecs.umich.edu for (int i = 0; i < 64; i++) { 4533880Ssaidi@eecs.umich.edu if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) 4543880Ssaidi@eecs.umich.edu diffTlb = true; 4553880Ssaidi@eecs.umich.edu if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) 4563880Ssaidi@eecs.umich.edu diffTlb = true; 4573880Ssaidi@eecs.umich.edu } 4583880Ssaidi@eecs.umich.edu 4594008Ssaidi@eecs.umich.edu if (diffPC || diffCC || diffInst || diffIntRegs || 4603931Ssaidi@eecs.umich.edu diffFpRegs || diffTpc || diffTnpc || diffTstate || 4613931Ssaidi@eecs.umich.edu diffTt || diffHpstate || diffHtstate || diffHtba || 4624001Ssaidi@eecs.umich.edu diffPstate || diffY || diffCcr || diffTl || diffFsr || 4634001Ssaidi@eecs.umich.edu diffGl || diffAsi || diffPil || diffCwp || diffCansave || 4643931Ssaidi@eecs.umich.edu diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) 4654008Ssaidi@eecs.umich.edu { 4663863Ssaidi@eecs.umich.edu 4673584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 4683584Ssaidi@eecs.umich.edu if (diffPC) 4693584Ssaidi@eecs.umich.edu outs << " [PC]"; 4703814Ssaidi@eecs.umich.edu if (diffCC) 4713814Ssaidi@eecs.umich.edu outs << " [CC]"; 4723584Ssaidi@eecs.umich.edu if (diffInst) 4733584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 4743931Ssaidi@eecs.umich.edu if (diffIntRegs) 4753584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4763931Ssaidi@eecs.umich.edu if (diffFpRegs) 4773931Ssaidi@eecs.umich.edu outs << " [FpRegs]"; 4783748Sgblack@eecs.umich.edu if (diffTpc) 4793748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4803748Sgblack@eecs.umich.edu if (diffTnpc) 4813748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 4823748Sgblack@eecs.umich.edu if (diffTstate) 4833748Sgblack@eecs.umich.edu outs << " [Tstate]"; 4843748Sgblack@eecs.umich.edu if (diffTt) 4853748Sgblack@eecs.umich.edu outs << " [Tt]"; 4863748Sgblack@eecs.umich.edu if (diffHpstate) 4873748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 4883748Sgblack@eecs.umich.edu if (diffHtstate) 4893748Sgblack@eecs.umich.edu outs << " [Htstate]"; 4903748Sgblack@eecs.umich.edu if (diffHtba) 4913748Sgblack@eecs.umich.edu outs << " [Htba]"; 4923748Sgblack@eecs.umich.edu if (diffPstate) 4933748Sgblack@eecs.umich.edu outs << " [Pstate]"; 4943748Sgblack@eecs.umich.edu if (diffY) 4953748Sgblack@eecs.umich.edu outs << " [Y]"; 4964001Ssaidi@eecs.umich.edu if (diffFsr) 4974001Ssaidi@eecs.umich.edu outs << " [FSR]"; 4983748Sgblack@eecs.umich.edu if (diffCcr) 4993748Sgblack@eecs.umich.edu outs << " [Ccr]"; 5003748Sgblack@eecs.umich.edu if (diffTl) 5013748Sgblack@eecs.umich.edu outs << " [Tl]"; 5023748Sgblack@eecs.umich.edu if (diffGl) 5033748Sgblack@eecs.umich.edu outs << " [Gl]"; 5043748Sgblack@eecs.umich.edu if (diffAsi) 5053748Sgblack@eecs.umich.edu outs << " [Asi]"; 5063748Sgblack@eecs.umich.edu if (diffPil) 5073748Sgblack@eecs.umich.edu outs << " [Pil]"; 5083748Sgblack@eecs.umich.edu if (diffCwp) 5093748Sgblack@eecs.umich.edu outs << " [Cwp]"; 5103748Sgblack@eecs.umich.edu if (diffCansave) 5113748Sgblack@eecs.umich.edu outs << " [Cansave]"; 5123748Sgblack@eecs.umich.edu if (diffCanrestore) 5133748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 5143748Sgblack@eecs.umich.edu if (diffOtherwin) 5153748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 5163748Sgblack@eecs.umich.edu if (diffCleanwin) 5173748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 5183880Ssaidi@eecs.umich.edu if (diffTlb) 5193880Ssaidi@eecs.umich.edu outs << " [Tlb]"; 5203603Ssaidi@eecs.umich.edu outs << endl << endl; 5213584Ssaidi@eecs.umich.edu 5223603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5233584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 5243603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 5253584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5263584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 5273603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 5283584Ssaidi@eecs.umich.edu 5293814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5303814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 5313814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 5323814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5333814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 5343814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 5353814Ssaidi@eecs.umich.edu 5363584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5373584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 5383584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 5393603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 5403584Ssaidi@eecs.umich.edu << endl; 5413584Ssaidi@eecs.umich.edu 5423748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 5433748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 5443748Sgblack@eecs.umich.edu thread)); 5453584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5463584Ssaidi@eecs.umich.edu << " Legion Inst: " 5473584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 5483584Ssaidi@eecs.umich.edu << shared_data->instruction 5493603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 5503748Sgblack@eecs.umich.edu << endl << endl; 5513584Ssaidi@eecs.umich.edu 5523748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 5533748Sgblack@eecs.umich.edu printColumnLabels(outs); 5543748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 5553748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HPSTATE), 5563748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 5573748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 5583748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTBA), 5593748Sgblack@eecs.umich.edu shared_data->htba); 5603748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 5613748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PSTATE), 5623748Sgblack@eecs.umich.edu shared_data->pstate); 5633748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 5643790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_Y), 5653989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1), 5663748Sgblack@eecs.umich.edu shared_data->y); 5674001Ssaidi@eecs.umich.edu printRegPair(outs, "FSR", 5684001Ssaidi@eecs.umich.edu thread->readMiscReg(MISCREG_FSR), 5694001Ssaidi@eecs.umich.edu shared_data->fsr); 5703748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 5713790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CCR), 5723989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2), 5733748Sgblack@eecs.umich.edu shared_data->ccr); 5743748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 5753748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TL), 5763748Sgblack@eecs.umich.edu shared_data->tl); 5773748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 5783748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_GL), 5793748Sgblack@eecs.umich.edu shared_data->gl); 5803748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 5813748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_ASI), 5823748Sgblack@eecs.umich.edu shared_data->asi); 5833748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 5843748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PIL), 5853748Sgblack@eecs.umich.edu shared_data->pil); 5863748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 5873748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CWP), 5883748Sgblack@eecs.umich.edu shared_data->cwp); 5893748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 5903790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CANSAVE), 5913790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3), 5923748Sgblack@eecs.umich.edu shared_data->cansave); 5933748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 5943790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CANRESTORE), 5953790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4), 5963748Sgblack@eecs.umich.edu shared_data->canrestore); 5973748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 5983790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_OTHERWIN), 5993989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6), 6003748Sgblack@eecs.umich.edu shared_data->otherwin); 6013748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 6023790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CLEANWIN), 6033989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5), 6043748Sgblack@eecs.umich.edu shared_data->cleanwin); 6053748Sgblack@eecs.umich.edu outs << endl; 6063748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 6073748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 6083748Sgblack@eecs.umich.edu printColumnLabels(outs); 6093748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 6103748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 6113748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TPC), 6123815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 6133748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 6143748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TNPC), 6153815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 6163748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 6173748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TSTATE), 6183815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 6193748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 6203748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TT), 6213815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 6223748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 6233748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTSTATE), 6243815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 6253748Sgblack@eecs.umich.edu } 6263748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 6273584Ssaidi@eecs.umich.edu outs << endl; 6283584Ssaidi@eecs.umich.edu 6293748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 6303584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 6313931Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) { 6323931Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) { 6333748Sgblack@eecs.umich.edu char label[8]; 6343748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 6353748Sgblack@eecs.umich.edu printRegPair(outs, label, 6363748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 6373748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 6383931Ssaidi@eecs.umich.edu } 6393931Ssaidi@eecs.umich.edu } 6403931Ssaidi@eecs.umich.edu if (diffFpRegs) { 6413931Ssaidi@eecs.umich.edu for (int x = 0; x < 32; x++) { 6423931Ssaidi@eecs.umich.edu char label[8]; 6433931Ssaidi@eecs.umich.edu sprintf(label, "%%f%d", x); 6443931Ssaidi@eecs.umich.edu printRegPair(outs, label, 6454008Ssaidi@eecs.umich.edu thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), 6463931Ssaidi@eecs.umich.edu shared_data->fpregs[x]); 6473584Ssaidi@eecs.umich.edu } 6483584Ssaidi@eecs.umich.edu } 6493903Ssaidi@eecs.umich.edu if (diffTlb) { 6503903Ssaidi@eecs.umich.edu printColumnLabels(outs); 6513903Ssaidi@eecs.umich.edu char label[8]; 6523903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6533903Ssaidi@eecs.umich.edu if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6543903Ssaidi@eecs.umich.edu thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6553903Ssaidi@eecs.umich.edu sprintf(label, "I-TLB:%02d", x); 6563903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getITBPtr()->TteRead(x), 6573903Ssaidi@eecs.umich.edu shared_data->itb[x]); 6583903Ssaidi@eecs.umich.edu } 6593880Ssaidi@eecs.umich.edu } 6603903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6613903Ssaidi@eecs.umich.edu if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6623903Ssaidi@eecs.umich.edu thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6633903Ssaidi@eecs.umich.edu sprintf(label, "D-TLB:%02d", x); 6643903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), 6653903Ssaidi@eecs.umich.edu shared_data->dtb[x]); 6663903Ssaidi@eecs.umich.edu } 6673903Ssaidi@eecs.umich.edu } 6683903Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 6693903Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 6703880Ssaidi@eecs.umich.edu } 6713826Ssaidi@eecs.umich.edu 6723825Ssaidi@eecs.umich.edu diffcount++; 6734011Ssaidi@eecs.umich.edu if (diffcount > 3) 6743825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 6753892Ssaidi@eecs.umich.edu } else 6763892Ssaidi@eecs.umich.edu diffcount = 0; 6773584Ssaidi@eecs.umich.edu 6783584Ssaidi@eecs.umich.edu compared = true; 6793584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 6803506Ssaidi@eecs.umich.edu } 6813584Ssaidi@eecs.umich.edu } // while 6823584Ssaidi@eecs.umich.edu } // if not microop 6833506Ssaidi@eecs.umich.edu } 6843584Ssaidi@eecs.umich.edu#endif 6852SN/A} 6862SN/A 6872SN/A 6882SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 6891967SN/Astring Trace::InstRecord::trace_system; 6902SN/A 6912SN/A//////////////////////////////////////////////////////////////////////// 6922SN/A// 6932SN/A// Parameter space for per-cycle execution address tracing options. 6942SN/A// Derive from ParamContext so we can override checkParams() function. 6952SN/A// 6962SN/Aclass ExecutionTraceParamContext : public ParamContext 6972SN/A{ 6982SN/A public: 6992SN/A ExecutionTraceParamContext(const string &_iniSection) 7002SN/A : ParamContext(_iniSection) 7012SN/A { 7022SN/A } 7032SN/A 7042SN/A void checkParams(); // defined at bottom of file 7052SN/A}; 7062SN/A 7072SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 7082SN/A 7092SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 7101413SN/A "capture speculative instructions", true); 7112SN/A 7122SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 7132SN/A "print cycle number", true); 7142SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 7152SN/A "print op class", true); 7162SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 7172SN/A "print thread number", true); 7182SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 7192SN/A "print effective address", true); 7202SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 7212SN/A "print result data", true); 7222SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 7232SN/A "print all integer regs", false); 7242SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 7252SN/A "print fetch sequence number", false); 7262SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 7272SN/A "print correct-path sequence number", false); 7282973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 7292973Sgblack@eecs.umich.edu "print which registers changed to what", false); 7302299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 7312299SN/A "Use symbols for the PC if available", true); 7321904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 7331904SN/A "print trace in intel compatible format", false); 7343506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 7353506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 7363506Ssaidi@eecs.umich.edu false); 7371967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 7381967SN/A "print trace of which system (client or server)", 7391967SN/A "client"); 7401904SN/A 7412SN/A 7422SN/A// 7432SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 7442SN/A// to get us into the InstRecord namespace 7452SN/A// 7462SN/Avoid 7472SN/ATrace::InstRecord::setParams() 7482SN/A{ 7492SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 7502SN/A 7512SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 7522SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 7532SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 7542SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 7552SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 7562SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 7572SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 7582SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 7592973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 7602299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 7611904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 7623506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 7631967SN/A trace_system = exe_trace_system; 7643506Ssaidi@eecs.umich.edu 7653506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 7663506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 7673506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 7683603Ssaidi@eecs.umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 7693506Ssaidi@eecs.umich.edu if (shmfd < 0) 7703506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 7713506Ssaidi@eecs.umich.edu 7723506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 7733506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 7743506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 7753506Ssaidi@eecs.umich.edu 7763506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 7773506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 7783506Ssaidi@eecs.umich.edu 7793506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 7803506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 7813506Ssaidi@eecs.umich.edu shared_data->version); 7823506Ssaidi@eecs.umich.edu 7833603Ssaidi@eecs.umich.edu // step legion forward one cycle so we can get register values 7843603Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 7853506Ssaidi@eecs.umich.edu } 7862SN/A} 7872SN/A 7882SN/Avoid 7892SN/AExecutionTraceParamContext::checkParams() 7902SN/A{ 7912SN/A Trace::InstRecord::setParams(); 7922SN/A} 7932SN/A 794