exetrace.cc revision 3945
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603840Shsul@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 613825Ssaidi@eecs.umich.edustatic int diffcount = 0; 623903Ssaidi@eecs.umich.edustatic bool wasMicro = false; 633840Shsul@eecs.umich.edu#endif 643825Ssaidi@eecs.umich.edu 653506Ssaidi@eecs.umich.edunamespace Trace { 663506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 673506Ssaidi@eecs.umich.edu} 683506Ssaidi@eecs.umich.edu 692SN/A//////////////////////////////////////////////////////////////////////// 702SN/A// 712SN/A// Methods for the InstRecord object 722SN/A// 732SN/A 743748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 753748Sgblack@eecs.umich.edu 763748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 773748Sgblack@eecs.umich.edu{ 783748Sgblack@eecs.umich.edu int labelLength = strlen(label); 793748Sgblack@eecs.umich.edu assert(labelLength <= length); 803748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 813748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 823748Sgblack@eecs.umich.edu char format[64]; 833748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 843748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 853748Sgblack@eecs.umich.edu return buffer; 863748Sgblack@eecs.umich.edu} 873748Sgblack@eecs.umich.edu 883748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 893748Sgblack@eecs.umich.edu{ 903748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 913748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 923748Sgblack@eecs.umich.edu} 933748Sgblack@eecs.umich.edu 943748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 953748Sgblack@eecs.umich.edu{ 963748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 973748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 983748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 993748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 1003748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 1013748Sgblack@eecs.umich.edu} 1023748Sgblack@eecs.umich.edu 1033748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1043748Sgblack@eecs.umich.edu{ 1053748Sgblack@eecs.umich.edu char sectionString[70]; 1063748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1073748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1083748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1093748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1103748Sgblack@eecs.umich.edu} 1113748Sgblack@eecs.umich.edu 1123748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1133748Sgblack@eecs.umich.edu{ 1143748Sgblack@eecs.umich.edu char sectionString[70]; 1153748Sgblack@eecs.umich.edu char levelName[70]; 1163748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1173748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1183748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1193748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1203748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1213748Sgblack@eecs.umich.edu} 1223748Sgblack@eecs.umich.edu 1233748Sgblack@eecs.umich.edu#endif 1242SN/A 1252SN/Avoid 1262SN/ATrace::InstRecord::dump(ostream &outs) 1272SN/A{ 1283903Ssaidi@eecs.umich.edu DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); 1292973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 1302973Sgblack@eecs.umich.edu { 1313065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1323380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1333380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1343380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1353380Sgblack@eecs.umich.edu { 1363380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1373380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1383380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1393380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1403380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1413380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1423380Sgblack@eecs.umich.edu static uint64_t y = 0; 1433380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1443380Sgblack@eecs.umich.edu uint64_t newVal; 1453380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1463065Sgblack@eecs.umich.edu 1473588Sgblack@eecs.umich.edu outs << hex; 1483588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1493588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1503380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 1513380Sgblack@eecs.umich.edu if(newVal != ccr) 1523059Sgblack@eecs.umich.edu { 1533588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1543380Sgblack@eecs.umich.edu ccr = newVal; 1553380Sgblack@eecs.umich.edu } 1563380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1573380Sgblack@eecs.umich.edu if(newVal != y) 1583380Sgblack@eecs.umich.edu { 1593588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1603380Sgblack@eecs.umich.edu y = newVal; 1613380Sgblack@eecs.umich.edu } 1623380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1633380Sgblack@eecs.umich.edu { 1643380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1653059Sgblack@eecs.umich.edu { 1663380Sgblack@eecs.umich.edu int index = x + 8 * y; 1673380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1683380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1693380Sgblack@eecs.umich.edu { 1703588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1713380Sgblack@eecs.umich.edu regs[index] = newVal; 1723380Sgblack@eecs.umich.edu } 1733059Sgblack@eecs.umich.edu } 1743059Sgblack@eecs.umich.edu } 1753380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1763380Sgblack@eecs.umich.edu { 1773380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1783380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1793380Sgblack@eecs.umich.edu { 1803588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1813380Sgblack@eecs.umich.edu floats[y] = newVal; 1823380Sgblack@eecs.umich.edu } 1833380Sgblack@eecs.umich.edu } 1843588Sgblack@eecs.umich.edu outs << dec << endl; 1853059Sgblack@eecs.umich.edu } 1863065Sgblack@eecs.umich.edu#endif 1872973Sgblack@eecs.umich.edu } 1882973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1891968SN/A#if FULL_SYSTEM 1903064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1911968SN/A#else 1921968SN/A bool is_trace_system = true; 1931968SN/A#endif 1941968SN/A if (is_trace_system) { 1951967SN/A ccprintf(outs, "%7d ) ", cycle); 1961967SN/A outs << "0x" << hex << PC << ":\t"; 1971967SN/A if (staticInst->isLoad()) { 1981967SN/A outs << "<RD 0x" << hex << addr; 1991967SN/A outs << ">"; 2001967SN/A } else if (staticInst->isStore()) { 2011967SN/A outs << "<WR 0x" << hex << addr; 2021967SN/A outs << ">"; 2031967SN/A } 2041967SN/A outs << endl; 2051904SN/A } 2061904SN/A } else { 2071904SN/A if (flags[PRINT_CYCLE]) 2081904SN/A ccprintf(outs, "%7d: ", cycle); 209452SN/A 2103064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2112SN/A 2121904SN/A if (flags[TRACE_MISSPEC]) 2131904SN/A outs << (misspeculating ? "-" : "+") << " "; 2142SN/A 2151904SN/A if (flags[PRINT_THREAD_NUM]) 2163064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2172SN/A 2182SN/A 2191904SN/A std::string sym_str; 2201904SN/A Addr sym_addr; 2211904SN/A if (debugSymbolTable 2222299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2232299SN/A && flags[PC_SYMBOL]) { 2241904SN/A if (PC != sym_addr) 2251904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2261904SN/A outs << "@" << sym_str << " : "; 2271904SN/A } 2281904SN/A else { 2291904SN/A outs << "0x" << hex << PC << " : "; 2301904SN/A } 231452SN/A 2321904SN/A // 2331904SN/A // Print decoded instruction 2341904SN/A // 2352SN/A 2362SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2371904SN/A // There's a bug in gcc 2.x library that prevents setw() 2381904SN/A // from working properly on strings 2391904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2401904SN/A while (mc.length() < 26) 2411904SN/A mc += " "; 2421904SN/A outs << mc; 2432SN/A#else 2441904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2452SN/A#endif 2462SN/A 2471904SN/A outs << " : "; 2482SN/A 2491904SN/A if (flags[PRINT_OP_CLASS]) { 2501904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2511904SN/A } 2521904SN/A 2531904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2541904SN/A outs << " D="; 2551904SN/A#if 0 2561904SN/A if (data_status == DataDouble) 2571904SN/A ccprintf(outs, "%f", data.as_double); 2581904SN/A else 2591904SN/A ccprintf(outs, "%#018x", data.as_int); 2601904SN/A#else 2611904SN/A ccprintf(outs, "%#018x", data.as_int); 2621904SN/A#endif 2631904SN/A } 2641904SN/A 2651904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2661904SN/A outs << " A=0x" << hex << addr; 2671904SN/A 2681904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2692525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2701904SN/A for (int j = i + 1; i <= j; i++) 2712525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2722525SN/A iregs->regs.readReg(i), 2732525SN/A ((i == j) ? "\n" : " ")); 2741904SN/A outs << "\n"; 2751904SN/A } 2761904SN/A 2771904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2781904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2791904SN/A 2801904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2811904SN/A outs << " CPSeq=" << dec << cp_seq; 2821967SN/A 2831967SN/A // 2841967SN/A // End of line... 2851967SN/A // 2861967SN/A outs << endl; 2872SN/A } 2883817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 2893506Ssaidi@eecs.umich.edu // Compare 2903506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2913506Ssaidi@eecs.umich.edu { 2923506Ssaidi@eecs.umich.edu bool compared = false; 2933506Ssaidi@eecs.umich.edu bool diffPC = false; 2943814Ssaidi@eecs.umich.edu bool diffCC = false; 2953506Ssaidi@eecs.umich.edu bool diffInst = false; 2963931Ssaidi@eecs.umich.edu bool diffIntRegs = false; 2973931Ssaidi@eecs.umich.edu bool diffFpRegs = false; 2983748Sgblack@eecs.umich.edu bool diffTpc = false; 2993748Sgblack@eecs.umich.edu bool diffTnpc = false; 3003748Sgblack@eecs.umich.edu bool diffTstate = false; 3013748Sgblack@eecs.umich.edu bool diffTt = false; 3023748Sgblack@eecs.umich.edu bool diffTba = false; 3033748Sgblack@eecs.umich.edu bool diffHpstate = false; 3043748Sgblack@eecs.umich.edu bool diffHtstate = false; 3053748Sgblack@eecs.umich.edu bool diffHtba = false; 3063748Sgblack@eecs.umich.edu bool diffPstate = false; 3073748Sgblack@eecs.umich.edu bool diffY = false; 3083748Sgblack@eecs.umich.edu bool diffCcr = false; 3093748Sgblack@eecs.umich.edu bool diffTl = false; 3103748Sgblack@eecs.umich.edu bool diffGl = false; 3113748Sgblack@eecs.umich.edu bool diffAsi = false; 3123748Sgblack@eecs.umich.edu bool diffPil = false; 3133748Sgblack@eecs.umich.edu bool diffCwp = false; 3143748Sgblack@eecs.umich.edu bool diffCansave = false; 3153748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3163748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3173748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3183880Ssaidi@eecs.umich.edu bool diffTlb = false; 3193603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3203603Ssaidi@eecs.umich.edu 3213903Ssaidi@eecs.umich.edu // We took a trap on a micro-op... 3223903Ssaidi@eecs.umich.edu if (wasMicro && !staticInst->isMicroOp()) 3233903Ssaidi@eecs.umich.edu { 3243903Ssaidi@eecs.umich.edu // let's skip comparing this cycle 3253903Ssaidi@eecs.umich.edu while (!compared) 3263903Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3273903Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3283903Ssaidi@eecs.umich.edu compared = true; 3293903Ssaidi@eecs.umich.edu } 3303903Ssaidi@eecs.umich.edu compared = false; 3313903Ssaidi@eecs.umich.edu wasMicro = false; 3323903Ssaidi@eecs.umich.edu } 3333903Ssaidi@eecs.umich.edu 3343903Ssaidi@eecs.umich.edu if (staticInst->isLastMicroOp()) 3353903Ssaidi@eecs.umich.edu wasMicro = false; 3363903Ssaidi@eecs.umich.edu else if (staticInst->isMicroOp()) 3373903Ssaidi@eecs.umich.edu wasMicro = true; 3383903Ssaidi@eecs.umich.edu 3393506Ssaidi@eecs.umich.edu 3403584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3413584Ssaidi@eecs.umich.edu while (!compared) { 3423584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3433748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3443928Ssaidi@eecs.umich.edu if (bits(shared_data->pstate,3,3)) { 3453928Ssaidi@eecs.umich.edu m5Pc &= mask(32); 3463928Ssaidi@eecs.umich.edu } 3473748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3483603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3493584Ssaidi@eecs.umich.edu diffPC = true; 3503814Ssaidi@eecs.umich.edu 3513814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 3523814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 3533814Ssaidi@eecs.umich.edu diffCC = true; 3543814Ssaidi@eecs.umich.edu 3553743Sgblack@eecs.umich.edu if (shared_data->instruction != 3563743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3573584Ssaidi@eecs.umich.edu diffInst = true; 3583743Sgblack@eecs.umich.edu } 3593754Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumIntArchRegs; i++) { 3603603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3613931Ssaidi@eecs.umich.edu diffIntRegs = true; 3623603Ssaidi@eecs.umich.edu } 3633584Ssaidi@eecs.umich.edu } 3643931Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { 3653945Ssaidi@eecs.umich.edu if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { 3663931Ssaidi@eecs.umich.edu diffFpRegs = true; 3673931Ssaidi@eecs.umich.edu } 3683931Ssaidi@eecs.umich.edu } 3693931Ssaidi@eecs.umich.edu uint64_t oldTl = thread->readMiscReg(MISCREG_TL); 3703748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3713748Sgblack@eecs.umich.edu diffTl = true; 3723748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3733748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 3743748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TPC) != 3753815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 3763748Sgblack@eecs.umich.edu diffTpc = true; 3773748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TNPC) != 3783815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 3793748Sgblack@eecs.umich.edu diffTnpc = true; 3803748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TSTATE) != 3813815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 3823748Sgblack@eecs.umich.edu diffTstate = true; 3833748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TT) != 3843815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 3853748Sgblack@eecs.umich.edu diffTt = true; 3863748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_HTSTATE) != 3873815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 3883748Sgblack@eecs.umich.edu diffHtstate = true; 3893748Sgblack@eecs.umich.edu } 3903748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 3913584Ssaidi@eecs.umich.edu 3923748Sgblack@eecs.umich.edu if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) 3933748Sgblack@eecs.umich.edu diffTba = true; 3943748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 3953748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 3963748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 3973748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 3983748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 3993748Sgblack@eecs.umich.edu //anyway. 4003748Sgblack@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) 4013748Sgblack@eecs.umich.edu diffHpstate = true; 4023748Sgblack@eecs.umich.edu if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) 4033748Sgblack@eecs.umich.edu diffHtba = true; 4043748Sgblack@eecs.umich.edu if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) 4053748Sgblack@eecs.umich.edu diffPstate = true; 4063748Sgblack@eecs.umich.edu if(shared_data->y != thread->readMiscReg(MISCREG_Y)) 4073748Sgblack@eecs.umich.edu diffY = true; 4083748Sgblack@eecs.umich.edu if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) 4093748Sgblack@eecs.umich.edu diffCcr = true; 4103748Sgblack@eecs.umich.edu if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) 4113748Sgblack@eecs.umich.edu diffGl = true; 4123748Sgblack@eecs.umich.edu if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) 4133748Sgblack@eecs.umich.edu diffAsi = true; 4143748Sgblack@eecs.umich.edu if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) 4153748Sgblack@eecs.umich.edu diffPil = true; 4163748Sgblack@eecs.umich.edu if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) 4173748Sgblack@eecs.umich.edu diffCwp = true; 4183748Sgblack@eecs.umich.edu if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) 4193748Sgblack@eecs.umich.edu diffCansave = true; 4203748Sgblack@eecs.umich.edu if(shared_data->canrestore != 4213748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE)) 4223748Sgblack@eecs.umich.edu diffCanrestore = true; 4233748Sgblack@eecs.umich.edu if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) 4243748Sgblack@eecs.umich.edu diffOtherwin = true; 4253748Sgblack@eecs.umich.edu if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) 4263748Sgblack@eecs.umich.edu diffCleanwin = true; 4273748Sgblack@eecs.umich.edu 4283880Ssaidi@eecs.umich.edu for (int i = 0; i < 64; i++) { 4293880Ssaidi@eecs.umich.edu if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) 4303880Ssaidi@eecs.umich.edu diffTlb = true; 4313880Ssaidi@eecs.umich.edu if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) 4323880Ssaidi@eecs.umich.edu diffTlb = true; 4333880Ssaidi@eecs.umich.edu } 4343880Ssaidi@eecs.umich.edu 4353931Ssaidi@eecs.umich.edu if ((diffPC || diffCC || diffInst || diffIntRegs || 4363931Ssaidi@eecs.umich.edu diffFpRegs || diffTpc || diffTnpc || diffTstate || 4373931Ssaidi@eecs.umich.edu diffTt || diffHpstate || diffHtstate || diffHtba || 4383931Ssaidi@eecs.umich.edu diffPstate || diffY || diffCcr || diffTl || diffGl || 4393931Ssaidi@eecs.umich.edu diffAsi || diffPil || diffCwp || diffCansave || 4403931Ssaidi@eecs.umich.edu diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) 4413863Ssaidi@eecs.umich.edu && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) 4423880Ssaidi@eecs.umich.edu && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) 4433880Ssaidi@eecs.umich.edu && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) 4443880Ssaidi@eecs.umich.edu ) { 4453863Ssaidi@eecs.umich.edu 4463584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 4473584Ssaidi@eecs.umich.edu if (diffPC) 4483584Ssaidi@eecs.umich.edu outs << " [PC]"; 4493814Ssaidi@eecs.umich.edu if (diffCC) 4503814Ssaidi@eecs.umich.edu outs << " [CC]"; 4513584Ssaidi@eecs.umich.edu if (diffInst) 4523584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 4533931Ssaidi@eecs.umich.edu if (diffIntRegs) 4543584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4553931Ssaidi@eecs.umich.edu if (diffFpRegs) 4563931Ssaidi@eecs.umich.edu outs << " [FpRegs]"; 4573748Sgblack@eecs.umich.edu if (diffTpc) 4583748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4593748Sgblack@eecs.umich.edu if (diffTnpc) 4603748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 4613748Sgblack@eecs.umich.edu if (diffTstate) 4623748Sgblack@eecs.umich.edu outs << " [Tstate]"; 4633748Sgblack@eecs.umich.edu if (diffTt) 4643748Sgblack@eecs.umich.edu outs << " [Tt]"; 4653748Sgblack@eecs.umich.edu if (diffHpstate) 4663748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 4673748Sgblack@eecs.umich.edu if (diffHtstate) 4683748Sgblack@eecs.umich.edu outs << " [Htstate]"; 4693748Sgblack@eecs.umich.edu if (diffHtba) 4703748Sgblack@eecs.umich.edu outs << " [Htba]"; 4713748Sgblack@eecs.umich.edu if (diffPstate) 4723748Sgblack@eecs.umich.edu outs << " [Pstate]"; 4733748Sgblack@eecs.umich.edu if (diffY) 4743748Sgblack@eecs.umich.edu outs << " [Y]"; 4753748Sgblack@eecs.umich.edu if (diffCcr) 4763748Sgblack@eecs.umich.edu outs << " [Ccr]"; 4773748Sgblack@eecs.umich.edu if (diffTl) 4783748Sgblack@eecs.umich.edu outs << " [Tl]"; 4793748Sgblack@eecs.umich.edu if (diffGl) 4803748Sgblack@eecs.umich.edu outs << " [Gl]"; 4813748Sgblack@eecs.umich.edu if (diffAsi) 4823748Sgblack@eecs.umich.edu outs << " [Asi]"; 4833748Sgblack@eecs.umich.edu if (diffPil) 4843748Sgblack@eecs.umich.edu outs << " [Pil]"; 4853748Sgblack@eecs.umich.edu if (diffCwp) 4863748Sgblack@eecs.umich.edu outs << " [Cwp]"; 4873748Sgblack@eecs.umich.edu if (diffCansave) 4883748Sgblack@eecs.umich.edu outs << " [Cansave]"; 4893748Sgblack@eecs.umich.edu if (diffCanrestore) 4903748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 4913748Sgblack@eecs.umich.edu if (diffOtherwin) 4923748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 4933748Sgblack@eecs.umich.edu if (diffCleanwin) 4943748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 4953880Ssaidi@eecs.umich.edu if (diffTlb) 4963880Ssaidi@eecs.umich.edu outs << " [Tlb]"; 4973603Ssaidi@eecs.umich.edu outs << endl << endl; 4983584Ssaidi@eecs.umich.edu 4993603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5003584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 5013603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 5023584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5033584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 5043603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 5053584Ssaidi@eecs.umich.edu 5063814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5073814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 5083814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 5093814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5103814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 5113814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 5123814Ssaidi@eecs.umich.edu 5133584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5143584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 5153584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 5163603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 5173584Ssaidi@eecs.umich.edu << endl; 5183584Ssaidi@eecs.umich.edu 5193748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 5203748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 5213748Sgblack@eecs.umich.edu thread)); 5223584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5233584Ssaidi@eecs.umich.edu << " Legion Inst: " 5243584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 5253584Ssaidi@eecs.umich.edu << shared_data->instruction 5263603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 5273748Sgblack@eecs.umich.edu << endl << endl; 5283584Ssaidi@eecs.umich.edu 5293748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 5303748Sgblack@eecs.umich.edu printColumnLabels(outs); 5313748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 5323748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HPSTATE), 5333748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 5343748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 5353748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTBA), 5363748Sgblack@eecs.umich.edu shared_data->htba); 5373748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 5383748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PSTATE), 5393748Sgblack@eecs.umich.edu shared_data->pstate); 5403748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 5413748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_Y), 5423748Sgblack@eecs.umich.edu shared_data->y); 5433748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 5443748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CCR), 5453748Sgblack@eecs.umich.edu shared_data->ccr); 5463748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 5473748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TL), 5483748Sgblack@eecs.umich.edu shared_data->tl); 5493748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 5503748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_GL), 5513748Sgblack@eecs.umich.edu shared_data->gl); 5523748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 5533748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_ASI), 5543748Sgblack@eecs.umich.edu shared_data->asi); 5553748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 5563748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PIL), 5573748Sgblack@eecs.umich.edu shared_data->pil); 5583748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 5593748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CWP), 5603748Sgblack@eecs.umich.edu shared_data->cwp); 5613748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 5623748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANSAVE), 5633748Sgblack@eecs.umich.edu shared_data->cansave); 5643748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 5653748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE), 5663748Sgblack@eecs.umich.edu shared_data->canrestore); 5673748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 5683748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_OTHERWIN), 5693748Sgblack@eecs.umich.edu shared_data->otherwin); 5703748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 5713748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CLEANWIN), 5723748Sgblack@eecs.umich.edu shared_data->cleanwin); 5733748Sgblack@eecs.umich.edu outs << endl; 5743748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 5753748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 5763748Sgblack@eecs.umich.edu printColumnLabels(outs); 5773748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 5783748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 5793748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TPC), 5803815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 5813748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 5823748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TNPC), 5833815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 5843748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 5853748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TSTATE), 5863815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 5873748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 5883748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TT), 5893815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 5903748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 5913748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTSTATE), 5923815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 5933748Sgblack@eecs.umich.edu } 5943748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 5953584Ssaidi@eecs.umich.edu outs << endl; 5963584Ssaidi@eecs.umich.edu 5973748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 5983584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 5993931Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) { 6003931Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) { 6013748Sgblack@eecs.umich.edu char label[8]; 6023748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 6033748Sgblack@eecs.umich.edu printRegPair(outs, label, 6043748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 6053748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 6063931Ssaidi@eecs.umich.edu } 6073931Ssaidi@eecs.umich.edu } 6083931Ssaidi@eecs.umich.edu if (diffFpRegs) { 6093931Ssaidi@eecs.umich.edu for (int x = 0; x < 32; x++) { 6103931Ssaidi@eecs.umich.edu char label[8]; 6113931Ssaidi@eecs.umich.edu sprintf(label, "%%f%d", x); 6123931Ssaidi@eecs.umich.edu printRegPair(outs, label, 6133931Ssaidi@eecs.umich.edu thread->readFloatRegBits(x,FloatRegFile::DoubleWidth), 6143931Ssaidi@eecs.umich.edu shared_data->fpregs[x]); 6153584Ssaidi@eecs.umich.edu } 6163584Ssaidi@eecs.umich.edu } 6173903Ssaidi@eecs.umich.edu if (diffTlb) { 6183903Ssaidi@eecs.umich.edu printColumnLabels(outs); 6193903Ssaidi@eecs.umich.edu char label[8]; 6203903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6213903Ssaidi@eecs.umich.edu if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6223903Ssaidi@eecs.umich.edu thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6233903Ssaidi@eecs.umich.edu sprintf(label, "I-TLB:%02d", x); 6243903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getITBPtr()->TteRead(x), 6253903Ssaidi@eecs.umich.edu shared_data->itb[x]); 6263903Ssaidi@eecs.umich.edu } 6273880Ssaidi@eecs.umich.edu } 6283903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6293903Ssaidi@eecs.umich.edu if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6303903Ssaidi@eecs.umich.edu thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6313903Ssaidi@eecs.umich.edu sprintf(label, "D-TLB:%02d", x); 6323903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), 6333903Ssaidi@eecs.umich.edu shared_data->dtb[x]); 6343903Ssaidi@eecs.umich.edu } 6353903Ssaidi@eecs.umich.edu } 6363903Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 6373903Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 6383880Ssaidi@eecs.umich.edu } 6393826Ssaidi@eecs.umich.edu 6403825Ssaidi@eecs.umich.edu diffcount++; 6413832Ssaidi@eecs.umich.edu if (diffcount > 2) 6423825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 6433892Ssaidi@eecs.umich.edu } else 6443892Ssaidi@eecs.umich.edu diffcount = 0; 6453584Ssaidi@eecs.umich.edu 6463584Ssaidi@eecs.umich.edu compared = true; 6473584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 6483506Ssaidi@eecs.umich.edu } 6493584Ssaidi@eecs.umich.edu } // while 6503584Ssaidi@eecs.umich.edu } // if not microop 6513506Ssaidi@eecs.umich.edu } 6523584Ssaidi@eecs.umich.edu#endif 6532SN/A} 6542SN/A 6552SN/A 6562SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 6571967SN/Astring Trace::InstRecord::trace_system; 6582SN/A 6592SN/A//////////////////////////////////////////////////////////////////////// 6602SN/A// 6612SN/A// Parameter space for per-cycle execution address tracing options. 6622SN/A// Derive from ParamContext so we can override checkParams() function. 6632SN/A// 6642SN/Aclass ExecutionTraceParamContext : public ParamContext 6652SN/A{ 6662SN/A public: 6672SN/A ExecutionTraceParamContext(const string &_iniSection) 6682SN/A : ParamContext(_iniSection) 6692SN/A { 6702SN/A } 6712SN/A 6722SN/A void checkParams(); // defined at bottom of file 6732SN/A}; 6742SN/A 6752SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 6762SN/A 6772SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 6781413SN/A "capture speculative instructions", true); 6792SN/A 6802SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 6812SN/A "print cycle number", true); 6822SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 6832SN/A "print op class", true); 6842SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 6852SN/A "print thread number", true); 6862SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 6872SN/A "print effective address", true); 6882SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 6892SN/A "print result data", true); 6902SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 6912SN/A "print all integer regs", false); 6922SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 6932SN/A "print fetch sequence number", false); 6942SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 6952SN/A "print correct-path sequence number", false); 6962973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 6972973Sgblack@eecs.umich.edu "print which registers changed to what", false); 6982299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 6992299SN/A "Use symbols for the PC if available", true); 7001904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 7011904SN/A "print trace in intel compatible format", false); 7023506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 7033506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 7043506Ssaidi@eecs.umich.edu false); 7051967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 7061967SN/A "print trace of which system (client or server)", 7071967SN/A "client"); 7081904SN/A 7092SN/A 7102SN/A// 7112SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 7122SN/A// to get us into the InstRecord namespace 7132SN/A// 7142SN/Avoid 7152SN/ATrace::InstRecord::setParams() 7162SN/A{ 7172SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 7182SN/A 7192SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 7202SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 7212SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 7222SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 7232SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 7242SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 7252SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 7262SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 7272973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 7282299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 7291904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 7303506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 7311967SN/A trace_system = exe_trace_system; 7323506Ssaidi@eecs.umich.edu 7333506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 7343506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 7353506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 7363603Ssaidi@eecs.umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 7373506Ssaidi@eecs.umich.edu if (shmfd < 0) 7383506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 7393506Ssaidi@eecs.umich.edu 7403506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 7413506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 7423506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 7433506Ssaidi@eecs.umich.edu 7443506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 7453506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 7463506Ssaidi@eecs.umich.edu 7473506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 7483506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 7493506Ssaidi@eecs.umich.edu shared_data->version); 7503506Ssaidi@eecs.umich.edu 7513603Ssaidi@eecs.umich.edu // step legion forward one cycle so we can get register values 7523603Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 7533506Ssaidi@eecs.umich.edu } 7542SN/A} 7552SN/A 7562SN/Avoid 7572SN/AExecutionTraceParamContext::checkParams() 7582SN/A{ 7592SN/A Trace::InstRecord::setParams(); 7602SN/A} 7612SN/A 762