exetrace.cc revision 3826
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603825Ssaidi@eecs.umich.edustatic int diffcount = 0; 613825Ssaidi@eecs.umich.edu 623506Ssaidi@eecs.umich.edunamespace Trace { 633506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 643506Ssaidi@eecs.umich.edu} 653506Ssaidi@eecs.umich.edu 662SN/A//////////////////////////////////////////////////////////////////////// 672SN/A// 682SN/A// Methods for the InstRecord object 692SN/A// 702SN/A 713748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 723748Sgblack@eecs.umich.edu 733748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 743748Sgblack@eecs.umich.edu{ 753748Sgblack@eecs.umich.edu int labelLength = strlen(label); 763748Sgblack@eecs.umich.edu assert(labelLength <= length); 773748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 783748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 793748Sgblack@eecs.umich.edu char format[64]; 803748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 813748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 823748Sgblack@eecs.umich.edu return buffer; 833748Sgblack@eecs.umich.edu} 843748Sgblack@eecs.umich.edu 853748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 863748Sgblack@eecs.umich.edu{ 873748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 883748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 893748Sgblack@eecs.umich.edu} 903748Sgblack@eecs.umich.edu 913748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 923748Sgblack@eecs.umich.edu{ 933748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 943748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 953748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 963748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 973748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 983748Sgblack@eecs.umich.edu} 993748Sgblack@eecs.umich.edu 1003748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1013748Sgblack@eecs.umich.edu{ 1023748Sgblack@eecs.umich.edu char sectionString[70]; 1033748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1043748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1053748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1063748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1073748Sgblack@eecs.umich.edu} 1083748Sgblack@eecs.umich.edu 1093748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1103748Sgblack@eecs.umich.edu{ 1113748Sgblack@eecs.umich.edu char sectionString[70]; 1123748Sgblack@eecs.umich.edu char levelName[70]; 1133748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1143748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1153748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1163748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1173748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1183748Sgblack@eecs.umich.edu} 1193748Sgblack@eecs.umich.edu 1203748Sgblack@eecs.umich.edu#endif 1212SN/A 1222SN/Avoid 1232SN/ATrace::InstRecord::dump(ostream &outs) 1242SN/A{ 1252973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 1262973Sgblack@eecs.umich.edu { 1273065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1283380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1293380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1303380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1313380Sgblack@eecs.umich.edu { 1323380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1333380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1343380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1353380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1363380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1373380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1383380Sgblack@eecs.umich.edu static uint64_t y = 0; 1393380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1403380Sgblack@eecs.umich.edu uint64_t newVal; 1413380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1423065Sgblack@eecs.umich.edu 1433588Sgblack@eecs.umich.edu outs << hex; 1443588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1453588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1463380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 1473380Sgblack@eecs.umich.edu if(newVal != ccr) 1483059Sgblack@eecs.umich.edu { 1493588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1503380Sgblack@eecs.umich.edu ccr = newVal; 1513380Sgblack@eecs.umich.edu } 1523380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1533380Sgblack@eecs.umich.edu if(newVal != y) 1543380Sgblack@eecs.umich.edu { 1553588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1563380Sgblack@eecs.umich.edu y = newVal; 1573380Sgblack@eecs.umich.edu } 1583380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1593380Sgblack@eecs.umich.edu { 1603380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1613059Sgblack@eecs.umich.edu { 1623380Sgblack@eecs.umich.edu int index = x + 8 * y; 1633380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1643380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1653380Sgblack@eecs.umich.edu { 1663588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1673380Sgblack@eecs.umich.edu regs[index] = newVal; 1683380Sgblack@eecs.umich.edu } 1693059Sgblack@eecs.umich.edu } 1703059Sgblack@eecs.umich.edu } 1713380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1723380Sgblack@eecs.umich.edu { 1733380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1743380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1753380Sgblack@eecs.umich.edu { 1763588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1773380Sgblack@eecs.umich.edu floats[y] = newVal; 1783380Sgblack@eecs.umich.edu } 1793380Sgblack@eecs.umich.edu } 1803588Sgblack@eecs.umich.edu outs << dec << endl; 1813059Sgblack@eecs.umich.edu } 1823065Sgblack@eecs.umich.edu#endif 1832973Sgblack@eecs.umich.edu } 1842973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1851968SN/A#if FULL_SYSTEM 1863064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1871968SN/A#else 1881968SN/A bool is_trace_system = true; 1891968SN/A#endif 1901968SN/A if (is_trace_system) { 1911967SN/A ccprintf(outs, "%7d ) ", cycle); 1921967SN/A outs << "0x" << hex << PC << ":\t"; 1931967SN/A if (staticInst->isLoad()) { 1941967SN/A outs << "<RD 0x" << hex << addr; 1951967SN/A outs << ">"; 1961967SN/A } else if (staticInst->isStore()) { 1971967SN/A outs << "<WR 0x" << hex << addr; 1981967SN/A outs << ">"; 1991967SN/A } 2001967SN/A outs << endl; 2011904SN/A } 2021904SN/A } else { 2031904SN/A if (flags[PRINT_CYCLE]) 2041904SN/A ccprintf(outs, "%7d: ", cycle); 205452SN/A 2063064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2072SN/A 2081904SN/A if (flags[TRACE_MISSPEC]) 2091904SN/A outs << (misspeculating ? "-" : "+") << " "; 2102SN/A 2111904SN/A if (flags[PRINT_THREAD_NUM]) 2123064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2132SN/A 2142SN/A 2151904SN/A std::string sym_str; 2161904SN/A Addr sym_addr; 2171904SN/A if (debugSymbolTable 2182299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2192299SN/A && flags[PC_SYMBOL]) { 2201904SN/A if (PC != sym_addr) 2211904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2221904SN/A outs << "@" << sym_str << " : "; 2231904SN/A } 2241904SN/A else { 2251904SN/A outs << "0x" << hex << PC << " : "; 2261904SN/A } 227452SN/A 2281904SN/A // 2291904SN/A // Print decoded instruction 2301904SN/A // 2312SN/A 2322SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2331904SN/A // There's a bug in gcc 2.x library that prevents setw() 2341904SN/A // from working properly on strings 2351904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2361904SN/A while (mc.length() < 26) 2371904SN/A mc += " "; 2381904SN/A outs << mc; 2392SN/A#else 2401904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2412SN/A#endif 2422SN/A 2431904SN/A outs << " : "; 2442SN/A 2451904SN/A if (flags[PRINT_OP_CLASS]) { 2461904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2471904SN/A } 2481904SN/A 2491904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2501904SN/A outs << " D="; 2511904SN/A#if 0 2521904SN/A if (data_status == DataDouble) 2531904SN/A ccprintf(outs, "%f", data.as_double); 2541904SN/A else 2551904SN/A ccprintf(outs, "%#018x", data.as_int); 2561904SN/A#else 2571904SN/A ccprintf(outs, "%#018x", data.as_int); 2581904SN/A#endif 2591904SN/A } 2601904SN/A 2611904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2621904SN/A outs << " A=0x" << hex << addr; 2631904SN/A 2641904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2652525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2661904SN/A for (int j = i + 1; i <= j; i++) 2672525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2682525SN/A iregs->regs.readReg(i), 2692525SN/A ((i == j) ? "\n" : " ")); 2701904SN/A outs << "\n"; 2711904SN/A } 2721904SN/A 2731904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2741904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2751904SN/A 2761904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2771904SN/A outs << " CPSeq=" << dec << cp_seq; 2781967SN/A 2791967SN/A // 2801967SN/A // End of line... 2811967SN/A // 2821967SN/A outs << endl; 2832SN/A } 2843817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 2853506Ssaidi@eecs.umich.edu // Compare 2863506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2873506Ssaidi@eecs.umich.edu { 2883506Ssaidi@eecs.umich.edu bool compared = false; 2893506Ssaidi@eecs.umich.edu bool diffPC = false; 2903814Ssaidi@eecs.umich.edu bool diffCC = false; 2913506Ssaidi@eecs.umich.edu bool diffInst = false; 2923506Ssaidi@eecs.umich.edu bool diffRegs = false; 2933748Sgblack@eecs.umich.edu bool diffTpc = false; 2943748Sgblack@eecs.umich.edu bool diffTnpc = false; 2953748Sgblack@eecs.umich.edu bool diffTstate = false; 2963748Sgblack@eecs.umich.edu bool diffTt = false; 2973748Sgblack@eecs.umich.edu bool diffTba = false; 2983748Sgblack@eecs.umich.edu bool diffHpstate = false; 2993748Sgblack@eecs.umich.edu bool diffHtstate = false; 3003748Sgblack@eecs.umich.edu bool diffHtba = false; 3013748Sgblack@eecs.umich.edu bool diffPstate = false; 3023748Sgblack@eecs.umich.edu bool diffY = false; 3033748Sgblack@eecs.umich.edu bool diffCcr = false; 3043748Sgblack@eecs.umich.edu bool diffTl = false; 3053748Sgblack@eecs.umich.edu bool diffGl = false; 3063748Sgblack@eecs.umich.edu bool diffAsi = false; 3073748Sgblack@eecs.umich.edu bool diffPil = false; 3083748Sgblack@eecs.umich.edu bool diffCwp = false; 3093748Sgblack@eecs.umich.edu bool diffCansave = false; 3103748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3113748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3123748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3133603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3143603Ssaidi@eecs.umich.edu 3153506Ssaidi@eecs.umich.edu 3163584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3173584Ssaidi@eecs.umich.edu while (!compared) { 3183584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3193748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3203748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3213603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3223584Ssaidi@eecs.umich.edu diffPC = true; 3233814Ssaidi@eecs.umich.edu 3243814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 3253814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 3263814Ssaidi@eecs.umich.edu diffCC = true; 3273814Ssaidi@eecs.umich.edu 3283743Sgblack@eecs.umich.edu if (shared_data->instruction != 3293743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3303584Ssaidi@eecs.umich.edu diffInst = true; 3313743Sgblack@eecs.umich.edu } 3323754Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumIntArchRegs; i++) { 3333603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3343584Ssaidi@eecs.umich.edu diffRegs = true; 3353603Ssaidi@eecs.umich.edu } 3363584Ssaidi@eecs.umich.edu } 3373748Sgblack@eecs.umich.edu uint64_t oldTl = thread->readMiscReg(MISCREG_TL); 3383748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3393748Sgblack@eecs.umich.edu diffTl = true; 3403748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3413748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 3423748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TPC) != 3433815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 3443748Sgblack@eecs.umich.edu diffTpc = true; 3453748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TNPC) != 3463815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 3473748Sgblack@eecs.umich.edu diffTnpc = true; 3483748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TSTATE) != 3493815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 3503748Sgblack@eecs.umich.edu diffTstate = true; 3513748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TT) != 3523815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 3533748Sgblack@eecs.umich.edu diffTt = true; 3543748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_HTSTATE) != 3553815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 3563748Sgblack@eecs.umich.edu diffHtstate = true; 3573748Sgblack@eecs.umich.edu } 3583748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 3593584Ssaidi@eecs.umich.edu 3603748Sgblack@eecs.umich.edu if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) 3613748Sgblack@eecs.umich.edu diffTba = true; 3623748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 3633748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 3643748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 3653748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 3663748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 3673748Sgblack@eecs.umich.edu //anyway. 3683748Sgblack@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) 3693748Sgblack@eecs.umich.edu diffHpstate = true; 3703748Sgblack@eecs.umich.edu if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) 3713748Sgblack@eecs.umich.edu diffHtba = true; 3723748Sgblack@eecs.umich.edu if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) 3733748Sgblack@eecs.umich.edu diffPstate = true; 3743748Sgblack@eecs.umich.edu if(shared_data->y != thread->readMiscReg(MISCREG_Y)) 3753748Sgblack@eecs.umich.edu diffY = true; 3763748Sgblack@eecs.umich.edu if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) 3773748Sgblack@eecs.umich.edu diffCcr = true; 3783748Sgblack@eecs.umich.edu if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) 3793748Sgblack@eecs.umich.edu diffGl = true; 3803748Sgblack@eecs.umich.edu if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) 3813748Sgblack@eecs.umich.edu diffAsi = true; 3823748Sgblack@eecs.umich.edu if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) 3833748Sgblack@eecs.umich.edu diffPil = true; 3843748Sgblack@eecs.umich.edu if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) 3853748Sgblack@eecs.umich.edu diffCwp = true; 3863748Sgblack@eecs.umich.edu if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) 3873748Sgblack@eecs.umich.edu diffCansave = true; 3883748Sgblack@eecs.umich.edu if(shared_data->canrestore != 3893748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE)) 3903748Sgblack@eecs.umich.edu diffCanrestore = true; 3913748Sgblack@eecs.umich.edu if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) 3923748Sgblack@eecs.umich.edu diffOtherwin = true; 3933748Sgblack@eecs.umich.edu if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) 3943748Sgblack@eecs.umich.edu diffCleanwin = true; 3953748Sgblack@eecs.umich.edu 3963826Ssaidi@eecs.umich.edu if ((diffPC || diffCC || diffInst || diffRegs || diffTpc || 3973814Ssaidi@eecs.umich.edu diffTnpc || diffTstate || diffTt || diffHpstate || 3983748Sgblack@eecs.umich.edu diffHtstate || diffHtba || diffPstate || diffY || 3993748Sgblack@eecs.umich.edu diffCcr || diffTl || diffGl || diffAsi || diffPil || 4003748Sgblack@eecs.umich.edu diffCwp || diffCansave || diffCanrestore || 4013826Ssaidi@eecs.umich.edu diffOtherwin || diffCleanwin) 4023826Ssaidi@eecs.umich.edu && !((staticInst->machInst & 0xE1F80000) == 0xE1F80000)) { 4033584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 4043584Ssaidi@eecs.umich.edu if (diffPC) 4053584Ssaidi@eecs.umich.edu outs << " [PC]"; 4063814Ssaidi@eecs.umich.edu if (diffCC) 4073814Ssaidi@eecs.umich.edu outs << " [CC]"; 4083584Ssaidi@eecs.umich.edu if (diffInst) 4093584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 4103584Ssaidi@eecs.umich.edu if (diffRegs) 4113584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4123748Sgblack@eecs.umich.edu if (diffTpc) 4133748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4143748Sgblack@eecs.umich.edu if (diffTnpc) 4153748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 4163748Sgblack@eecs.umich.edu if (diffTstate) 4173748Sgblack@eecs.umich.edu outs << " [Tstate]"; 4183748Sgblack@eecs.umich.edu if (diffTt) 4193748Sgblack@eecs.umich.edu outs << " [Tt]"; 4203748Sgblack@eecs.umich.edu if (diffHpstate) 4213748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 4223748Sgblack@eecs.umich.edu if (diffHtstate) 4233748Sgblack@eecs.umich.edu outs << " [Htstate]"; 4243748Sgblack@eecs.umich.edu if (diffHtba) 4253748Sgblack@eecs.umich.edu outs << " [Htba]"; 4263748Sgblack@eecs.umich.edu if (diffPstate) 4273748Sgblack@eecs.umich.edu outs << " [Pstate]"; 4283748Sgblack@eecs.umich.edu if (diffY) 4293748Sgblack@eecs.umich.edu outs << " [Y]"; 4303748Sgblack@eecs.umich.edu if (diffCcr) 4313748Sgblack@eecs.umich.edu outs << " [Ccr]"; 4323748Sgblack@eecs.umich.edu if (diffTl) 4333748Sgblack@eecs.umich.edu outs << " [Tl]"; 4343748Sgblack@eecs.umich.edu if (diffGl) 4353748Sgblack@eecs.umich.edu outs << " [Gl]"; 4363748Sgblack@eecs.umich.edu if (diffAsi) 4373748Sgblack@eecs.umich.edu outs << " [Asi]"; 4383748Sgblack@eecs.umich.edu if (diffPil) 4393748Sgblack@eecs.umich.edu outs << " [Pil]"; 4403748Sgblack@eecs.umich.edu if (diffCwp) 4413748Sgblack@eecs.umich.edu outs << " [Cwp]"; 4423748Sgblack@eecs.umich.edu if (diffCansave) 4433748Sgblack@eecs.umich.edu outs << " [Cansave]"; 4443748Sgblack@eecs.umich.edu if (diffCanrestore) 4453748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 4463748Sgblack@eecs.umich.edu if (diffOtherwin) 4473748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 4483748Sgblack@eecs.umich.edu if (diffCleanwin) 4493748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 4503603Ssaidi@eecs.umich.edu outs << endl << endl; 4513584Ssaidi@eecs.umich.edu 4523603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 4533584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 4543603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 4553584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4563584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 4573603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 4583584Ssaidi@eecs.umich.edu 4593814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 4603814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 4613814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 4623814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4633814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 4643814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 4653814Ssaidi@eecs.umich.edu 4663584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4673584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 4683584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 4693603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 4703584Ssaidi@eecs.umich.edu << endl; 4713584Ssaidi@eecs.umich.edu 4723748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 4733748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 4743748Sgblack@eecs.umich.edu thread)); 4753584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4763584Ssaidi@eecs.umich.edu << " Legion Inst: " 4773584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 4783584Ssaidi@eecs.umich.edu << shared_data->instruction 4793603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 4803748Sgblack@eecs.umich.edu << endl << endl; 4813584Ssaidi@eecs.umich.edu 4823748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 4833748Sgblack@eecs.umich.edu printColumnLabels(outs); 4843748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 4853748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HPSTATE), 4863748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 4873748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 4883748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTBA), 4893748Sgblack@eecs.umich.edu shared_data->htba); 4903748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 4913748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PSTATE), 4923748Sgblack@eecs.umich.edu shared_data->pstate); 4933748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 4943748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_Y), 4953748Sgblack@eecs.umich.edu shared_data->y); 4963748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 4973748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CCR), 4983748Sgblack@eecs.umich.edu shared_data->ccr); 4993748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 5003748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TL), 5013748Sgblack@eecs.umich.edu shared_data->tl); 5023748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 5033748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_GL), 5043748Sgblack@eecs.umich.edu shared_data->gl); 5053748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 5063748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_ASI), 5073748Sgblack@eecs.umich.edu shared_data->asi); 5083748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 5093748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PIL), 5103748Sgblack@eecs.umich.edu shared_data->pil); 5113748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 5123748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CWP), 5133748Sgblack@eecs.umich.edu shared_data->cwp); 5143748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 5153748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANSAVE), 5163748Sgblack@eecs.umich.edu shared_data->cansave); 5173748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 5183748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE), 5193748Sgblack@eecs.umich.edu shared_data->canrestore); 5203748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 5213748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_OTHERWIN), 5223748Sgblack@eecs.umich.edu shared_data->otherwin); 5233748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 5243748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CLEANWIN), 5253748Sgblack@eecs.umich.edu shared_data->cleanwin); 5263748Sgblack@eecs.umich.edu outs << endl; 5273748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 5283748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 5293748Sgblack@eecs.umich.edu printColumnLabels(outs); 5303748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 5313748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 5323748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TPC), 5333815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 5343748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 5353748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TNPC), 5363815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 5373748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 5383748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TSTATE), 5393815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 5403748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 5413748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TT), 5423815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 5433748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 5443748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTSTATE), 5453815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 5463748Sgblack@eecs.umich.edu } 5473748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 5483584Ssaidi@eecs.umich.edu outs << endl; 5493584Ssaidi@eecs.umich.edu 5503748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 5513584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 5523584Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) 5533584Ssaidi@eecs.umich.edu { 5543584Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) 5553584Ssaidi@eecs.umich.edu { 5563748Sgblack@eecs.umich.edu char label[8]; 5573748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 5583748Sgblack@eecs.umich.edu printRegPair(outs, label, 5593748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 5603748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 5613748Sgblack@eecs.umich.edu /*outs << regtypes[y] << x << " " ; 5623748Sgblack@eecs.umich.edu outs << "0x" << hex << setw(16) 5633748Sgblack@eecs.umich.edu << thread->readIntReg(y*8+x); 5643748Sgblack@eecs.umich.edu if (thread->readIntReg(y*8 + x) 5653748Sgblack@eecs.umich.edu != shared_data->intregs[y*8+x]) 5663584Ssaidi@eecs.umich.edu outs << " X "; 5673584Ssaidi@eecs.umich.edu else 5683584Ssaidi@eecs.umich.edu outs << " | "; 5693748Sgblack@eecs.umich.edu outs << "0x" << setw(16) << hex 5703748Sgblack@eecs.umich.edu << shared_data->intregs[y*8+x] 5713748Sgblack@eecs.umich.edu << endl;*/ 5723584Ssaidi@eecs.umich.edu } 5733584Ssaidi@eecs.umich.edu } 5743826Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 5753826Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 5763826Ssaidi@eecs.umich.edu 5773825Ssaidi@eecs.umich.edu diffcount++; 5783825Ssaidi@eecs.umich.edu if (diffcount > 3) 5793825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 5803584Ssaidi@eecs.umich.edu } 5813584Ssaidi@eecs.umich.edu 5823584Ssaidi@eecs.umich.edu compared = true; 5833584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 5843506Ssaidi@eecs.umich.edu } 5853584Ssaidi@eecs.umich.edu } // while 5863584Ssaidi@eecs.umich.edu } // if not microop 5873506Ssaidi@eecs.umich.edu } 5883584Ssaidi@eecs.umich.edu#endif 5892SN/A} 5902SN/A 5912SN/A 5922SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 5931967SN/Astring Trace::InstRecord::trace_system; 5942SN/A 5952SN/A//////////////////////////////////////////////////////////////////////// 5962SN/A// 5972SN/A// Parameter space for per-cycle execution address tracing options. 5982SN/A// Derive from ParamContext so we can override checkParams() function. 5992SN/A// 6002SN/Aclass ExecutionTraceParamContext : public ParamContext 6012SN/A{ 6022SN/A public: 6032SN/A ExecutionTraceParamContext(const string &_iniSection) 6042SN/A : ParamContext(_iniSection) 6052SN/A { 6062SN/A } 6072SN/A 6082SN/A void checkParams(); // defined at bottom of file 6092SN/A}; 6102SN/A 6112SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 6122SN/A 6132SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 6141413SN/A "capture speculative instructions", true); 6152SN/A 6162SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 6172SN/A "print cycle number", true); 6182SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 6192SN/A "print op class", true); 6202SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 6212SN/A "print thread number", true); 6222SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 6232SN/A "print effective address", true); 6242SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 6252SN/A "print result data", true); 6262SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 6272SN/A "print all integer regs", false); 6282SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 6292SN/A "print fetch sequence number", false); 6302SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 6312SN/A "print correct-path sequence number", false); 6322973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 6332973Sgblack@eecs.umich.edu "print which registers changed to what", false); 6342299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 6352299SN/A "Use symbols for the PC if available", true); 6361904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 6371904SN/A "print trace in intel compatible format", false); 6383506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 6393506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 6403506Ssaidi@eecs.umich.edu false); 6411967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 6421967SN/A "print trace of which system (client or server)", 6431967SN/A "client"); 6441904SN/A 6452SN/A 6462SN/A// 6472SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 6482SN/A// to get us into the InstRecord namespace 6492SN/A// 6502SN/Avoid 6512SN/ATrace::InstRecord::setParams() 6522SN/A{ 6532SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 6542SN/A 6552SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 6562SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 6572SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 6582SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 6592SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 6602SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 6612SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 6622SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 6632973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 6642299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 6651904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 6663506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 6671967SN/A trace_system = exe_trace_system; 6683506Ssaidi@eecs.umich.edu 6693506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 6703506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 6713506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 6723603Ssaidi@eecs.umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 6733506Ssaidi@eecs.umich.edu if (shmfd < 0) 6743506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 6753506Ssaidi@eecs.umich.edu 6763506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 6773506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 6783506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 6793506Ssaidi@eecs.umich.edu 6803506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 6813506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 6823506Ssaidi@eecs.umich.edu 6833506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 6843506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 6853506Ssaidi@eecs.umich.edu shared_data->version); 6863506Ssaidi@eecs.umich.edu 6873603Ssaidi@eecs.umich.edu // step legion forward one cycle so we can get register values 6883603Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 6893506Ssaidi@eecs.umich.edu } 6902SN/A} 6912SN/A 6922SN/Avoid 6932SN/AExecutionTraceParamContext::checkParams() 6942SN/A{ 6952SN/A Trace::InstRecord::setParams(); 6962SN/A} 6972SN/A 698