exetrace.cc revision 3614
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603506Ssaidi@eecs.umich.edunamespace Trace { 613506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 623506Ssaidi@eecs.umich.edu} 633506Ssaidi@eecs.umich.edu 642SN/A//////////////////////////////////////////////////////////////////////// 652SN/A// 662SN/A// Methods for the InstRecord object 672SN/A// 682SN/A 692SN/A 702SN/Avoid 712SN/ATrace::InstRecord::dump(ostream &outs) 722SN/A{ 732973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 742973Sgblack@eecs.umich.edu { 753065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 763380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 773380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 783380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 793380Sgblack@eecs.umich.edu { 803380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 813380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 823380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 833380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 843380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 853380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 863380Sgblack@eecs.umich.edu static uint64_t y = 0; 873380Sgblack@eecs.umich.edu static uint64_t floats[32]; 883380Sgblack@eecs.umich.edu uint64_t newVal; 893380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 903065Sgblack@eecs.umich.edu 913588Sgblack@eecs.umich.edu outs << hex; 923588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 933588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 943380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 953380Sgblack@eecs.umich.edu if(newVal != ccr) 963059Sgblack@eecs.umich.edu { 973588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 983380Sgblack@eecs.umich.edu ccr = newVal; 993380Sgblack@eecs.umich.edu } 1003380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1013380Sgblack@eecs.umich.edu if(newVal != y) 1023380Sgblack@eecs.umich.edu { 1033588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1043380Sgblack@eecs.umich.edu y = newVal; 1053380Sgblack@eecs.umich.edu } 1063380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1073380Sgblack@eecs.umich.edu { 1083380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1093059Sgblack@eecs.umich.edu { 1103380Sgblack@eecs.umich.edu int index = x + 8 * y; 1113380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1123380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1133380Sgblack@eecs.umich.edu { 1143588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1153380Sgblack@eecs.umich.edu regs[index] = newVal; 1163380Sgblack@eecs.umich.edu } 1173059Sgblack@eecs.umich.edu } 1183059Sgblack@eecs.umich.edu } 1193380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1203380Sgblack@eecs.umich.edu { 1213380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1223380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1233380Sgblack@eecs.umich.edu { 1243588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1253380Sgblack@eecs.umich.edu floats[y] = newVal; 1263380Sgblack@eecs.umich.edu } 1273380Sgblack@eecs.umich.edu } 1283588Sgblack@eecs.umich.edu outs << dec << endl; 1293059Sgblack@eecs.umich.edu } 1303065Sgblack@eecs.umich.edu#endif 1312973Sgblack@eecs.umich.edu } 1322973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1331968SN/A#if FULL_SYSTEM 1343064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1351968SN/A#else 1361968SN/A bool is_trace_system = true; 1371968SN/A#endif 1381968SN/A if (is_trace_system) { 1391967SN/A ccprintf(outs, "%7d ) ", cycle); 1401967SN/A outs << "0x" << hex << PC << ":\t"; 1411967SN/A if (staticInst->isLoad()) { 1421967SN/A outs << "<RD 0x" << hex << addr; 1431967SN/A outs << ">"; 1441967SN/A } else if (staticInst->isStore()) { 1451967SN/A outs << "<WR 0x" << hex << addr; 1461967SN/A outs << ">"; 1471967SN/A } 1481967SN/A outs << endl; 1491904SN/A } 1501904SN/A } else { 1511904SN/A if (flags[PRINT_CYCLE]) 1521904SN/A ccprintf(outs, "%7d: ", cycle); 153452SN/A 1543064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 1552SN/A 1561904SN/A if (flags[TRACE_MISSPEC]) 1571904SN/A outs << (misspeculating ? "-" : "+") << " "; 1582SN/A 1591904SN/A if (flags[PRINT_THREAD_NUM]) 1603064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 1612SN/A 1622SN/A 1631904SN/A std::string sym_str; 1641904SN/A Addr sym_addr; 1651904SN/A if (debugSymbolTable 1662299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1672299SN/A && flags[PC_SYMBOL]) { 1681904SN/A if (PC != sym_addr) 1691904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1701904SN/A outs << "@" << sym_str << " : "; 1711904SN/A } 1721904SN/A else { 1731904SN/A outs << "0x" << hex << PC << " : "; 1741904SN/A } 175452SN/A 1761904SN/A // 1771904SN/A // Print decoded instruction 1781904SN/A // 1792SN/A 1802SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1811904SN/A // There's a bug in gcc 2.x library that prevents setw() 1821904SN/A // from working properly on strings 1831904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1841904SN/A while (mc.length() < 26) 1851904SN/A mc += " "; 1861904SN/A outs << mc; 1872SN/A#else 1881904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1892SN/A#endif 1902SN/A 1911904SN/A outs << " : "; 1922SN/A 1931904SN/A if (flags[PRINT_OP_CLASS]) { 1941904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1951904SN/A } 1961904SN/A 1971904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1981904SN/A outs << " D="; 1991904SN/A#if 0 2001904SN/A if (data_status == DataDouble) 2011904SN/A ccprintf(outs, "%f", data.as_double); 2021904SN/A else 2031904SN/A ccprintf(outs, "%#018x", data.as_int); 2041904SN/A#else 2051904SN/A ccprintf(outs, "%#018x", data.as_int); 2061904SN/A#endif 2071904SN/A } 2081904SN/A 2091904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2101904SN/A outs << " A=0x" << hex << addr; 2111904SN/A 2121904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2132525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2141904SN/A for (int j = i + 1; i <= j; i++) 2152525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2162525SN/A iregs->regs.readReg(i), 2172525SN/A ((i == j) ? "\n" : " ")); 2181904SN/A outs << "\n"; 2191904SN/A } 2201904SN/A 2211904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2221904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2231904SN/A 2241904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2251904SN/A outs << " CPSeq=" << dec << cp_seq; 2261967SN/A 2271967SN/A // 2281967SN/A // End of line... 2291967SN/A // 2301967SN/A outs << endl; 2312SN/A } 2323584Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA 2333506Ssaidi@eecs.umich.edu // Compare 2343506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2353506Ssaidi@eecs.umich.edu { 2363506Ssaidi@eecs.umich.edu bool compared = false; 2373506Ssaidi@eecs.umich.edu bool diffPC = false; 2383506Ssaidi@eecs.umich.edu bool diffInst = false; 2393506Ssaidi@eecs.umich.edu bool diffRegs = false; 2403603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 2413603Ssaidi@eecs.umich.edu 2423506Ssaidi@eecs.umich.edu 2433584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 2443584Ssaidi@eecs.umich.edu while (!compared) { 2453603Ssaidi@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 2463603Ssaidi@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 2473584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 2483603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 2493584Ssaidi@eecs.umich.edu diffPC = true; 2503584Ssaidi@eecs.umich.edu if (shared_data->instruction != staticInst->machInst) 2513584Ssaidi@eecs.umich.edu diffInst = true; 2523603Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumRegularIntRegs; i++) { 2533603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 2543584Ssaidi@eecs.umich.edu diffRegs = true; 2553603Ssaidi@eecs.umich.edu } 2563584Ssaidi@eecs.umich.edu } 2573584Ssaidi@eecs.umich.edu 2583584Ssaidi@eecs.umich.edu if (diffPC || diffInst || diffRegs ) { 2593584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 2603584Ssaidi@eecs.umich.edu if (diffPC) 2613584Ssaidi@eecs.umich.edu outs << " [PC]"; 2623584Ssaidi@eecs.umich.edu if (diffInst) 2633584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 2643584Ssaidi@eecs.umich.edu if (diffRegs) 2653584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 2663603Ssaidi@eecs.umich.edu outs << endl << endl; 2673584Ssaidi@eecs.umich.edu 2683603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 2693584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 2703603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 2713584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2723584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 2733603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 2743584Ssaidi@eecs.umich.edu 2753584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2763584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 2773584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 2783603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 2793584Ssaidi@eecs.umich.edu << endl; 2803584Ssaidi@eecs.umich.edu 2813584Ssaidi@eecs.umich.edu StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread)); 2823584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2833584Ssaidi@eecs.umich.edu << " Legion Inst: " 2843584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 2853584Ssaidi@eecs.umich.edu << shared_data->instruction 2863603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 2873584Ssaidi@eecs.umich.edu << endl; 2883584Ssaidi@eecs.umich.edu 2893584Ssaidi@eecs.umich.edu outs << endl; 2903584Ssaidi@eecs.umich.edu 2913584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 2923584Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) 2933584Ssaidi@eecs.umich.edu { 2943584Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) 2953584Ssaidi@eecs.umich.edu { 2963584Ssaidi@eecs.umich.edu outs << regtypes[y] << x << " " ; 2973584Ssaidi@eecs.umich.edu outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x); 2983584Ssaidi@eecs.umich.edu if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x]) 2993584Ssaidi@eecs.umich.edu outs << " X "; 3003584Ssaidi@eecs.umich.edu else 3013584Ssaidi@eecs.umich.edu outs << " | "; 3023584Ssaidi@eecs.umich.edu outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x] 3033584Ssaidi@eecs.umich.edu << endl; 3043584Ssaidi@eecs.umich.edu } 3053584Ssaidi@eecs.umich.edu } 3063584Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 3073584Ssaidi@eecs.umich.edu } 3083584Ssaidi@eecs.umich.edu 3093584Ssaidi@eecs.umich.edu compared = true; 3103584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3113506Ssaidi@eecs.umich.edu } 3123584Ssaidi@eecs.umich.edu } // while 3133584Ssaidi@eecs.umich.edu } // if not microop 3143506Ssaidi@eecs.umich.edu } 3153584Ssaidi@eecs.umich.edu#endif 3162SN/A} 3172SN/A 3182SN/A 3192SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 3201967SN/Astring Trace::InstRecord::trace_system; 3212SN/A 3222SN/A//////////////////////////////////////////////////////////////////////// 3232SN/A// 3242SN/A// Parameter space for per-cycle execution address tracing options. 3252SN/A// Derive from ParamContext so we can override checkParams() function. 3262SN/A// 3272SN/Aclass ExecutionTraceParamContext : public ParamContext 3282SN/A{ 3292SN/A public: 3302SN/A ExecutionTraceParamContext(const string &_iniSection) 3312SN/A : ParamContext(_iniSection) 3322SN/A { 3332SN/A } 3342SN/A 3352SN/A void checkParams(); // defined at bottom of file 3362SN/A}; 3372SN/A 3382SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 3392SN/A 3402SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 3411413SN/A "capture speculative instructions", true); 3422SN/A 3432SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 3442SN/A "print cycle number", true); 3452SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 3462SN/A "print op class", true); 3472SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 3482SN/A "print thread number", true); 3492SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 3502SN/A "print effective address", true); 3512SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 3522SN/A "print result data", true); 3532SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 3542SN/A "print all integer regs", false); 3552SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 3562SN/A "print fetch sequence number", false); 3572SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 3582SN/A "print correct-path sequence number", false); 3592973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 3602973Sgblack@eecs.umich.edu "print which registers changed to what", false); 3612299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 3622299SN/A "Use symbols for the PC if available", true); 3631904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 3641904SN/A "print trace in intel compatible format", false); 3653506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 3663506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 3673506Ssaidi@eecs.umich.edu false); 3681967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 3691967SN/A "print trace of which system (client or server)", 3701967SN/A "client"); 3711904SN/A 3722SN/A 3732SN/A// 3742SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 3752SN/A// to get us into the InstRecord namespace 3762SN/A// 3772SN/Avoid 3782SN/ATrace::InstRecord::setParams() 3792SN/A{ 3802SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 3812SN/A 3822SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 3832SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 3842SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 3852SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 3862SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 3872SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 3882SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 3892SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 3902973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 3912299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 3921904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 3933506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 3941967SN/A trace_system = exe_trace_system; 3953506Ssaidi@eecs.umich.edu 3963506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 3973506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 3983506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 3993603Ssaidi@eecs.umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 4003506Ssaidi@eecs.umich.edu if (shmfd < 0) 4013506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 4023506Ssaidi@eecs.umich.edu 4033506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 4043506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 4053506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 4063506Ssaidi@eecs.umich.edu 4073506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 4083506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 4093506Ssaidi@eecs.umich.edu 4103506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 4113506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 4123506Ssaidi@eecs.umich.edu shared_data->version); 4133506Ssaidi@eecs.umich.edu 4143603Ssaidi@eecs.umich.edu // step legion forward one cycle so we can get register values 4153603Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 4163506Ssaidi@eecs.umich.edu } 4172SN/A} 4182SN/A 4192SN/Avoid 4202SN/AExecutionTraceParamContext::checkParams() 4212SN/A{ 4222SN/A Trace::InstRecord::setParams(); 4232SN/A} 4242SN/A 425