exetrace.cc revision 3588
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 421717SN/A#include "cpu/base.hh" 432518SN/A#include "cpu/exetrace.hh" 4456SN/A#include "cpu/static_inst.hh" 452518SN/A#include "sim/param.hh" 462518SN/A#include "sim/system.hh" 472SN/A 483065Sgblack@eecs.umich.edu//XXX This is temporary 493065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 503506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 513065Sgblack@eecs.umich.edu 522SN/Ausing namespace std; 532973Sgblack@eecs.umich.eduusing namespace TheISA; 542SN/A 553506Ssaidi@eecs.umich.edunamespace Trace { 563506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 573506Ssaidi@eecs.umich.edu} 583506Ssaidi@eecs.umich.edu 592SN/A//////////////////////////////////////////////////////////////////////// 602SN/A// 612SN/A// Methods for the InstRecord object 622SN/A// 632SN/A 642SN/A 652SN/Avoid 662SN/ATrace::InstRecord::dump(ostream &outs) 672SN/A{ 682973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 692973Sgblack@eecs.umich.edu { 703065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 713380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 723380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 733380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 743380Sgblack@eecs.umich.edu { 753380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 763380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 773380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 783380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 793380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 803380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 813380Sgblack@eecs.umich.edu static uint64_t y = 0; 823380Sgblack@eecs.umich.edu static uint64_t floats[32]; 833380Sgblack@eecs.umich.edu uint64_t newVal; 843380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 853065Sgblack@eecs.umich.edu 863588Sgblack@eecs.umich.edu outs << hex; 873588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 883588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 893380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 903380Sgblack@eecs.umich.edu if(newVal != ccr) 913059Sgblack@eecs.umich.edu { 923588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 933380Sgblack@eecs.umich.edu ccr = newVal; 943380Sgblack@eecs.umich.edu } 953380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 963380Sgblack@eecs.umich.edu if(newVal != y) 973380Sgblack@eecs.umich.edu { 983588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 993380Sgblack@eecs.umich.edu y = newVal; 1003380Sgblack@eecs.umich.edu } 1013380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1023380Sgblack@eecs.umich.edu { 1033380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1043059Sgblack@eecs.umich.edu { 1053380Sgblack@eecs.umich.edu int index = x + 8 * y; 1063380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1073380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1083380Sgblack@eecs.umich.edu { 1093588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1103380Sgblack@eecs.umich.edu regs[index] = newVal; 1113380Sgblack@eecs.umich.edu } 1123059Sgblack@eecs.umich.edu } 1133059Sgblack@eecs.umich.edu } 1143380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1153380Sgblack@eecs.umich.edu { 1163380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1173380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1183380Sgblack@eecs.umich.edu { 1193588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1203380Sgblack@eecs.umich.edu floats[y] = newVal; 1213380Sgblack@eecs.umich.edu } 1223380Sgblack@eecs.umich.edu } 1233588Sgblack@eecs.umich.edu outs << dec << endl; 1243059Sgblack@eecs.umich.edu } 1253065Sgblack@eecs.umich.edu#endif 1262973Sgblack@eecs.umich.edu } 1272973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1281968SN/A#if FULL_SYSTEM 1293064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1301968SN/A#else 1311968SN/A bool is_trace_system = true; 1321968SN/A#endif 1331968SN/A if (is_trace_system) { 1341967SN/A ccprintf(outs, "%7d ) ", cycle); 1351967SN/A outs << "0x" << hex << PC << ":\t"; 1361967SN/A if (staticInst->isLoad()) { 1371967SN/A outs << "<RD 0x" << hex << addr; 1381967SN/A outs << ">"; 1391967SN/A } else if (staticInst->isStore()) { 1401967SN/A outs << "<WR 0x" << hex << addr; 1411967SN/A outs << ">"; 1421967SN/A } 1431967SN/A outs << endl; 1441904SN/A } 1451904SN/A } else { 1461904SN/A if (flags[PRINT_CYCLE]) 1471904SN/A ccprintf(outs, "%7d: ", cycle); 148452SN/A 1493064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 1502SN/A 1511904SN/A if (flags[TRACE_MISSPEC]) 1521904SN/A outs << (misspeculating ? "-" : "+") << " "; 1532SN/A 1541904SN/A if (flags[PRINT_THREAD_NUM]) 1553064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 1562SN/A 1572SN/A 1581904SN/A std::string sym_str; 1591904SN/A Addr sym_addr; 1601904SN/A if (debugSymbolTable 1612299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1622299SN/A && flags[PC_SYMBOL]) { 1631904SN/A if (PC != sym_addr) 1641904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1651904SN/A outs << "@" << sym_str << " : "; 1661904SN/A } 1671904SN/A else { 1681904SN/A outs << "0x" << hex << PC << " : "; 1691904SN/A } 170452SN/A 1711904SN/A // 1721904SN/A // Print decoded instruction 1731904SN/A // 1742SN/A 1752SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1761904SN/A // There's a bug in gcc 2.x library that prevents setw() 1771904SN/A // from working properly on strings 1781904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1791904SN/A while (mc.length() < 26) 1801904SN/A mc += " "; 1811904SN/A outs << mc; 1822SN/A#else 1831904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1842SN/A#endif 1852SN/A 1861904SN/A outs << " : "; 1872SN/A 1881904SN/A if (flags[PRINT_OP_CLASS]) { 1891904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1901904SN/A } 1911904SN/A 1921904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1931904SN/A outs << " D="; 1941904SN/A#if 0 1951904SN/A if (data_status == DataDouble) 1961904SN/A ccprintf(outs, "%f", data.as_double); 1971904SN/A else 1981904SN/A ccprintf(outs, "%#018x", data.as_int); 1991904SN/A#else 2001904SN/A ccprintf(outs, "%#018x", data.as_int); 2011904SN/A#endif 2021904SN/A } 2031904SN/A 2041904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2051904SN/A outs << " A=0x" << hex << addr; 2061904SN/A 2071904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2082525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2091904SN/A for (int j = i + 1; i <= j; i++) 2102525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2112525SN/A iregs->regs.readReg(i), 2122525SN/A ((i == j) ? "\n" : " ")); 2131904SN/A outs << "\n"; 2141904SN/A } 2151904SN/A 2161904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2171904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2181904SN/A 2191904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2201904SN/A outs << " CPSeq=" << dec << cp_seq; 2211967SN/A 2221967SN/A // 2231967SN/A // End of line... 2241967SN/A // 2251967SN/A outs << endl; 2262SN/A } 2273584Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA 2283506Ssaidi@eecs.umich.edu // Compare 2293506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2303506Ssaidi@eecs.umich.edu { 2313506Ssaidi@eecs.umich.edu bool compared = false; 2323506Ssaidi@eecs.umich.edu bool diffPC = false; 2333506Ssaidi@eecs.umich.edu bool diffInst = false; 2343506Ssaidi@eecs.umich.edu bool diffRegs = false; 2353506Ssaidi@eecs.umich.edu 2363584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 2373584Ssaidi@eecs.umich.edu while (!compared) { 2383584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 2393584Ssaidi@eecs.umich.edu if (shared_data->pc != PC) 2403584Ssaidi@eecs.umich.edu diffPC = true; 2413584Ssaidi@eecs.umich.edu if (shared_data->instruction != staticInst->machInst) 2423584Ssaidi@eecs.umich.edu diffInst = true; 2433584Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; i++) { 2443584Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) 2453584Ssaidi@eecs.umich.edu diffRegs = true; 2463584Ssaidi@eecs.umich.edu } 2473584Ssaidi@eecs.umich.edu 2483584Ssaidi@eecs.umich.edu if (diffPC || diffInst || diffRegs ) { 2493584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 2503584Ssaidi@eecs.umich.edu if (diffPC) 2513584Ssaidi@eecs.umich.edu outs << " [PC]"; 2523584Ssaidi@eecs.umich.edu if (diffInst) 2533584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 2543584Ssaidi@eecs.umich.edu if (diffRegs) 2553584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 2563584Ssaidi@eecs.umich.edu outs << endl << endl;; 2573584Ssaidi@eecs.umich.edu 2583584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2593584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 2603584Ssaidi@eecs.umich.edu << hex << PC << endl; 2613584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2623584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 2633584Ssaidi@eecs.umich.edu << shared_data->pc << endl << endl; 2643584Ssaidi@eecs.umich.edu 2653584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2663584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 2673584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 2683584Ssaidi@eecs.umich.edu << staticInst->disassemble(PC, debugSymbolTable) 2693584Ssaidi@eecs.umich.edu << endl; 2703584Ssaidi@eecs.umich.edu 2713584Ssaidi@eecs.umich.edu StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread)); 2723584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 2733584Ssaidi@eecs.umich.edu << " Legion Inst: " 2743584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 2753584Ssaidi@eecs.umich.edu << shared_data->instruction 2763584Ssaidi@eecs.umich.edu << legionInst->disassemble(shared_data->pc, debugSymbolTable) 2773584Ssaidi@eecs.umich.edu << endl; 2783584Ssaidi@eecs.umich.edu 2793584Ssaidi@eecs.umich.edu outs << endl; 2803584Ssaidi@eecs.umich.edu 2813584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 2823584Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) 2833584Ssaidi@eecs.umich.edu { 2843584Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) 2853584Ssaidi@eecs.umich.edu { 2863584Ssaidi@eecs.umich.edu outs << regtypes[y] << x << " " ; 2873584Ssaidi@eecs.umich.edu outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x); 2883584Ssaidi@eecs.umich.edu if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x]) 2893584Ssaidi@eecs.umich.edu outs << " X "; 2903584Ssaidi@eecs.umich.edu else 2913584Ssaidi@eecs.umich.edu outs << " | "; 2923584Ssaidi@eecs.umich.edu outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x] 2933584Ssaidi@eecs.umich.edu << endl; 2943584Ssaidi@eecs.umich.edu } 2953584Ssaidi@eecs.umich.edu } 2963584Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 2973584Ssaidi@eecs.umich.edu } 2983584Ssaidi@eecs.umich.edu 2993584Ssaidi@eecs.umich.edu compared = true; 3003584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3013506Ssaidi@eecs.umich.edu } 3023584Ssaidi@eecs.umich.edu } // while 3033584Ssaidi@eecs.umich.edu } // if not microop 3043506Ssaidi@eecs.umich.edu } 3053584Ssaidi@eecs.umich.edu#endif 3062SN/A} 3072SN/A 3082SN/A 3092SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 3101967SN/Astring Trace::InstRecord::trace_system; 3112SN/A 3122SN/A//////////////////////////////////////////////////////////////////////// 3132SN/A// 3142SN/A// Parameter space for per-cycle execution address tracing options. 3152SN/A// Derive from ParamContext so we can override checkParams() function. 3162SN/A// 3172SN/Aclass ExecutionTraceParamContext : public ParamContext 3182SN/A{ 3192SN/A public: 3202SN/A ExecutionTraceParamContext(const string &_iniSection) 3212SN/A : ParamContext(_iniSection) 3222SN/A { 3232SN/A } 3242SN/A 3252SN/A void checkParams(); // defined at bottom of file 3262SN/A}; 3272SN/A 3282SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 3292SN/A 3302SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 3311413SN/A "capture speculative instructions", true); 3322SN/A 3332SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 3342SN/A "print cycle number", true); 3352SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 3362SN/A "print op class", true); 3372SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 3382SN/A "print thread number", true); 3392SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 3402SN/A "print effective address", true); 3412SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 3422SN/A "print result data", true); 3432SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 3442SN/A "print all integer regs", false); 3452SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 3462SN/A "print fetch sequence number", false); 3472SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 3482SN/A "print correct-path sequence number", false); 3492973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 3502973Sgblack@eecs.umich.edu "print which registers changed to what", false); 3512299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 3522299SN/A "Use symbols for the PC if available", true); 3531904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 3541904SN/A "print trace in intel compatible format", false); 3553506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 3563506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 3573506Ssaidi@eecs.umich.edu false); 3581967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 3591967SN/A "print trace of which system (client or server)", 3601967SN/A "client"); 3611904SN/A 3622SN/A 3632SN/A// 3642SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 3652SN/A// to get us into the InstRecord namespace 3662SN/A// 3672SN/Avoid 3682SN/ATrace::InstRecord::setParams() 3692SN/A{ 3702SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 3712SN/A 3722SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 3732SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 3742SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 3752SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 3762SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 3772SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 3782SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 3792SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 3802973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 3812299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 3821904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 3833506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 3841967SN/A trace_system = exe_trace_system; 3853506Ssaidi@eecs.umich.edu 3863506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 3873506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 3883506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 3893506Ssaidi@eecs.umich.edu int shmfd = shmget(getuid(), sizeof(SharedData), 0777); 3903506Ssaidi@eecs.umich.edu if (shmfd < 0) 3913506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 3923506Ssaidi@eecs.umich.edu 3933506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 3943506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 3953506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 3963506Ssaidi@eecs.umich.edu 3973506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 3983506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 3993506Ssaidi@eecs.umich.edu 4003506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 4013506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 4023506Ssaidi@eecs.umich.edu shared_data->version); 4033506Ssaidi@eecs.umich.edu 4043506Ssaidi@eecs.umich.edu } 4052SN/A} 4062SN/A 4072SN/Avoid 4082SN/AExecutionTraceParamContext::checkParams() 4092SN/A{ 4102SN/A Trace::InstRecord::setParams(); 4112SN/A} 4122SN/A 413