exetrace.cc revision 3380
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 362SN/A 372973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 3856SN/A#include "base/loader/symtab.hh" 391717SN/A#include "cpu/base.hh" 402518SN/A#include "cpu/exetrace.hh" 4156SN/A#include "cpu/static_inst.hh" 422518SN/A#include "sim/param.hh" 432518SN/A#include "sim/system.hh" 442SN/A 453065Sgblack@eecs.umich.edu//XXX This is temporary 463065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 473065Sgblack@eecs.umich.edu 482SN/Ausing namespace std; 492973Sgblack@eecs.umich.eduusing namespace TheISA; 502SN/A 512SN/A//////////////////////////////////////////////////////////////////////// 522SN/A// 532SN/A// Methods for the InstRecord object 542SN/A// 552SN/A 562SN/A 572SN/Avoid 582SN/ATrace::InstRecord::dump(ostream &outs) 592SN/A{ 602973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 612973Sgblack@eecs.umich.edu { 623065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 633380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 643380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 653380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 663380Sgblack@eecs.umich.edu { 673380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 683380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 693380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 703380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 713380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 723380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 733380Sgblack@eecs.umich.edu static uint64_t y = 0; 743380Sgblack@eecs.umich.edu static uint64_t floats[32]; 753380Sgblack@eecs.umich.edu uint64_t newVal; 763380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 773065Sgblack@eecs.umich.edu 783380Sgblack@eecs.umich.edu char buf[256]; 793380Sgblack@eecs.umich.edu sprintf(buf, "PC = 0x%016llx", thread->readNextPC()); 803059Sgblack@eecs.umich.edu outs << buf; 813380Sgblack@eecs.umich.edu sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC()); 823059Sgblack@eecs.umich.edu outs << buf; 833380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 843380Sgblack@eecs.umich.edu if(newVal != ccr) 853059Sgblack@eecs.umich.edu { 863380Sgblack@eecs.umich.edu sprintf(buf, " CCR = 0x%016llx", newVal); 873380Sgblack@eecs.umich.edu outs << buf; 883380Sgblack@eecs.umich.edu ccr = newVal; 893380Sgblack@eecs.umich.edu } 903380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 913380Sgblack@eecs.umich.edu if(newVal != y) 923380Sgblack@eecs.umich.edu { 933380Sgblack@eecs.umich.edu sprintf(buf, " Y = 0x%016llx", newVal); 943380Sgblack@eecs.umich.edu outs << buf; 953380Sgblack@eecs.umich.edu y = newVal; 963380Sgblack@eecs.umich.edu } 973380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 983380Sgblack@eecs.umich.edu { 993380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1003059Sgblack@eecs.umich.edu { 1013380Sgblack@eecs.umich.edu int index = x + 8 * y; 1023380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1033380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1043380Sgblack@eecs.umich.edu { 1053380Sgblack@eecs.umich.edu sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal); 1063380Sgblack@eecs.umich.edu outs << buf; 1073380Sgblack@eecs.umich.edu regs[index] = newVal; 1083380Sgblack@eecs.umich.edu } 1093059Sgblack@eecs.umich.edu } 1103059Sgblack@eecs.umich.edu } 1113380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1123380Sgblack@eecs.umich.edu { 1133380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1143380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1153380Sgblack@eecs.umich.edu { 1163380Sgblack@eecs.umich.edu sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal); 1173380Sgblack@eecs.umich.edu outs << buf; 1183380Sgblack@eecs.umich.edu floats[y] = newVal; 1193380Sgblack@eecs.umich.edu } 1203380Sgblack@eecs.umich.edu } 1213380Sgblack@eecs.umich.edu outs << endl; 1223059Sgblack@eecs.umich.edu } 1233065Sgblack@eecs.umich.edu#endif 1242973Sgblack@eecs.umich.edu } 1252973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1261968SN/A#if FULL_SYSTEM 1273064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1281968SN/A#else 1291968SN/A bool is_trace_system = true; 1301968SN/A#endif 1311968SN/A if (is_trace_system) { 1321967SN/A ccprintf(outs, "%7d ) ", cycle); 1331967SN/A outs << "0x" << hex << PC << ":\t"; 1341967SN/A if (staticInst->isLoad()) { 1351967SN/A outs << "<RD 0x" << hex << addr; 1361967SN/A outs << ">"; 1371967SN/A } else if (staticInst->isStore()) { 1381967SN/A outs << "<WR 0x" << hex << addr; 1391967SN/A outs << ">"; 1401967SN/A } 1411967SN/A outs << endl; 1421904SN/A } 1431904SN/A } else { 1441904SN/A if (flags[PRINT_CYCLE]) 1451904SN/A ccprintf(outs, "%7d: ", cycle); 146452SN/A 1473064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 1482SN/A 1491904SN/A if (flags[TRACE_MISSPEC]) 1501904SN/A outs << (misspeculating ? "-" : "+") << " "; 1512SN/A 1521904SN/A if (flags[PRINT_THREAD_NUM]) 1533064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 1542SN/A 1552SN/A 1561904SN/A std::string sym_str; 1571904SN/A Addr sym_addr; 1581904SN/A if (debugSymbolTable 1592299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1602299SN/A && flags[PC_SYMBOL]) { 1611904SN/A if (PC != sym_addr) 1621904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1631904SN/A outs << "@" << sym_str << " : "; 1641904SN/A } 1651904SN/A else { 1661904SN/A outs << "0x" << hex << PC << " : "; 1671904SN/A } 168452SN/A 1691904SN/A // 1701904SN/A // Print decoded instruction 1711904SN/A // 1722SN/A 1732SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1741904SN/A // There's a bug in gcc 2.x library that prevents setw() 1751904SN/A // from working properly on strings 1761904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1771904SN/A while (mc.length() < 26) 1781904SN/A mc += " "; 1791904SN/A outs << mc; 1802SN/A#else 1811904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1822SN/A#endif 1832SN/A 1841904SN/A outs << " : "; 1852SN/A 1861904SN/A if (flags[PRINT_OP_CLASS]) { 1871904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1881904SN/A } 1891904SN/A 1901904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1911904SN/A outs << " D="; 1921904SN/A#if 0 1931904SN/A if (data_status == DataDouble) 1941904SN/A ccprintf(outs, "%f", data.as_double); 1951904SN/A else 1961904SN/A ccprintf(outs, "%#018x", data.as_int); 1971904SN/A#else 1981904SN/A ccprintf(outs, "%#018x", data.as_int); 1991904SN/A#endif 2001904SN/A } 2011904SN/A 2021904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2031904SN/A outs << " A=0x" << hex << addr; 2041904SN/A 2051904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2062525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2071904SN/A for (int j = i + 1; i <= j; i++) 2082525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2092525SN/A iregs->regs.readReg(i), 2102525SN/A ((i == j) ? "\n" : " ")); 2111904SN/A outs << "\n"; 2121904SN/A } 2131904SN/A 2141904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2151904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2161904SN/A 2171904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2181904SN/A outs << " CPSeq=" << dec << cp_seq; 2191967SN/A 2201967SN/A // 2211967SN/A // End of line... 2221967SN/A // 2231967SN/A outs << endl; 2242SN/A } 2252SN/A} 2262SN/A 2272SN/A 2282SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 2291967SN/Astring Trace::InstRecord::trace_system; 2302SN/A 2312SN/A//////////////////////////////////////////////////////////////////////// 2322SN/A// 2332SN/A// Parameter space for per-cycle execution address tracing options. 2342SN/A// Derive from ParamContext so we can override checkParams() function. 2352SN/A// 2362SN/Aclass ExecutionTraceParamContext : public ParamContext 2372SN/A{ 2382SN/A public: 2392SN/A ExecutionTraceParamContext(const string &_iniSection) 2402SN/A : ParamContext(_iniSection) 2412SN/A { 2422SN/A } 2432SN/A 2442SN/A void checkParams(); // defined at bottom of file 2452SN/A}; 2462SN/A 2472SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 2482SN/A 2492SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 2501413SN/A "capture speculative instructions", true); 2512SN/A 2522SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 2532SN/A "print cycle number", true); 2542SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 2552SN/A "print op class", true); 2562SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 2572SN/A "print thread number", true); 2582SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 2592SN/A "print effective address", true); 2602SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 2612SN/A "print result data", true); 2622SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 2632SN/A "print all integer regs", false); 2642SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 2652SN/A "print fetch sequence number", false); 2662SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 2672SN/A "print correct-path sequence number", false); 2682973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 2692973Sgblack@eecs.umich.edu "print which registers changed to what", false); 2702299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 2712299SN/A "Use symbols for the PC if available", true); 2721904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 2731904SN/A "print trace in intel compatible format", false); 2741967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 2751967SN/A "print trace of which system (client or server)", 2761967SN/A "client"); 2771904SN/A 2782SN/A 2792SN/A// 2802SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 2812SN/A// to get us into the InstRecord namespace 2822SN/A// 2832SN/Avoid 2842SN/ATrace::InstRecord::setParams() 2852SN/A{ 2862SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 2872SN/A 2882SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 2892SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 2902SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 2912SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 2922SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 2932SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 2942SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 2952SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 2962973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 2972299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 2981904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 2991967SN/A trace_system = exe_trace_system; 3002SN/A} 3012SN/A 3022SN/Avoid 3032SN/AExecutionTraceParamContext::checkParams() 3042SN/A{ 3052SN/A Trace::InstRecord::setParams(); 3062SN/A} 3072SN/A 308