exetrace.cc revision 3064
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 362SN/A 372973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 3856SN/A#include "base/loader/symtab.hh" 391717SN/A#include "cpu/base.hh" 402518SN/A#include "cpu/exetrace.hh" 4156SN/A#include "cpu/static_inst.hh" 422518SN/A#include "sim/param.hh" 432518SN/A#include "sim/system.hh" 442SN/A 452SN/Ausing namespace std; 462973Sgblack@eecs.umich.eduusing namespace TheISA; 472SN/A 482SN/A//////////////////////////////////////////////////////////////////////// 492SN/A// 502SN/A// Methods for the InstRecord object 512SN/A// 522SN/A 532SN/A 542SN/Avoid 552SN/ATrace::InstRecord::dump(ostream &outs) 562SN/A{ 573059Sgblack@eecs.umich.edu static uint64_t regs[32] = { 583059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 593059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 603059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 613059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 623059Sgblack@eecs.umich.edu static uint64_t ccr = 0; 633059Sgblack@eecs.umich.edu static uint64_t y = 0; 643059Sgblack@eecs.umich.edu static uint64_t floats[32]; 653059Sgblack@eecs.umich.edu uint64_t newVal; 663059Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 672973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 682973Sgblack@eecs.umich.edu { 693059Sgblack@eecs.umich.edu char buf[256]; 703064Sgblack@eecs.umich.edu sprintf(buf, "PC = 0x%016llx", thread->readNextPC()); 713059Sgblack@eecs.umich.edu outs << buf; 723064Sgblack@eecs.umich.edu sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC()); 733059Sgblack@eecs.umich.edu outs << buf; 743064Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 753059Sgblack@eecs.umich.edu if(newVal != ccr) 763059Sgblack@eecs.umich.edu { 773059Sgblack@eecs.umich.edu sprintf(buf, " CCR = 0x%016llx", newVal); 783059Sgblack@eecs.umich.edu outs << buf; 793059Sgblack@eecs.umich.edu ccr = newVal; 803059Sgblack@eecs.umich.edu } 813064Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 823059Sgblack@eecs.umich.edu if(newVal != y) 833059Sgblack@eecs.umich.edu { 843059Sgblack@eecs.umich.edu sprintf(buf, " Y = 0x%016llx", newVal); 853059Sgblack@eecs.umich.edu outs << buf; 863059Sgblack@eecs.umich.edu y = newVal; 873059Sgblack@eecs.umich.edu } 883059Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 893059Sgblack@eecs.umich.edu { 903059Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 913059Sgblack@eecs.umich.edu { 923059Sgblack@eecs.umich.edu int index = x + 8 * y; 933064Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 943059Sgblack@eecs.umich.edu if(regs[index] != newVal) 953059Sgblack@eecs.umich.edu { 963059Sgblack@eecs.umich.edu sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal); 973059Sgblack@eecs.umich.edu outs << buf; 983059Sgblack@eecs.umich.edu regs[index] = newVal; 993059Sgblack@eecs.umich.edu } 1003059Sgblack@eecs.umich.edu } 1013059Sgblack@eecs.umich.edu } 1023059Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1033059Sgblack@eecs.umich.edu { 1043064Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1053059Sgblack@eecs.umich.edu if(floats[y] != newVal) 1063059Sgblack@eecs.umich.edu { 1073059Sgblack@eecs.umich.edu sprintf(buf, " F%d = 0x%016llx", y, newVal); 1083059Sgblack@eecs.umich.edu outs << buf; 1093059Sgblack@eecs.umich.edu floats[y] = newVal; 1103059Sgblack@eecs.umich.edu } 1113059Sgblack@eecs.umich.edu } 1123059Sgblack@eecs.umich.edu outs << endl; 1132973Sgblack@eecs.umich.edu } 1142973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1151968SN/A#if FULL_SYSTEM 1163064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1171968SN/A#else 1181968SN/A bool is_trace_system = true; 1191968SN/A#endif 1201968SN/A if (is_trace_system) { 1211967SN/A ccprintf(outs, "%7d ) ", cycle); 1221967SN/A outs << "0x" << hex << PC << ":\t"; 1231967SN/A if (staticInst->isLoad()) { 1241967SN/A outs << "<RD 0x" << hex << addr; 1251967SN/A outs << ">"; 1261967SN/A } else if (staticInst->isStore()) { 1271967SN/A outs << "<WR 0x" << hex << addr; 1281967SN/A outs << ">"; 1291967SN/A } 1301967SN/A outs << endl; 1311904SN/A } 1321904SN/A } else { 1331904SN/A if (flags[PRINT_CYCLE]) 1341904SN/A ccprintf(outs, "%7d: ", cycle); 135452SN/A 1363064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 1372SN/A 1381904SN/A if (flags[TRACE_MISSPEC]) 1391904SN/A outs << (misspeculating ? "-" : "+") << " "; 1402SN/A 1411904SN/A if (flags[PRINT_THREAD_NUM]) 1423064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 1432SN/A 1442SN/A 1451904SN/A std::string sym_str; 1461904SN/A Addr sym_addr; 1471904SN/A if (debugSymbolTable 1482299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1492299SN/A && flags[PC_SYMBOL]) { 1501904SN/A if (PC != sym_addr) 1511904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1521904SN/A outs << "@" << sym_str << " : "; 1531904SN/A } 1541904SN/A else { 1551904SN/A outs << "0x" << hex << PC << " : "; 1561904SN/A } 157452SN/A 1581904SN/A // 1591904SN/A // Print decoded instruction 1601904SN/A // 1612SN/A 1622SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1631904SN/A // There's a bug in gcc 2.x library that prevents setw() 1641904SN/A // from working properly on strings 1651904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1661904SN/A while (mc.length() < 26) 1671904SN/A mc += " "; 1681904SN/A outs << mc; 1692SN/A#else 1701904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1712SN/A#endif 1722SN/A 1731904SN/A outs << " : "; 1742SN/A 1751904SN/A if (flags[PRINT_OP_CLASS]) { 1761904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1771904SN/A } 1781904SN/A 1791904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1801904SN/A outs << " D="; 1811904SN/A#if 0 1821904SN/A if (data_status == DataDouble) 1831904SN/A ccprintf(outs, "%f", data.as_double); 1841904SN/A else 1851904SN/A ccprintf(outs, "%#018x", data.as_int); 1861904SN/A#else 1871904SN/A ccprintf(outs, "%#018x", data.as_int); 1881904SN/A#endif 1891904SN/A } 1901904SN/A 1911904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 1921904SN/A outs << " A=0x" << hex << addr; 1931904SN/A 1941904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 1952525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 1961904SN/A for (int j = i + 1; i <= j; i++) 1972525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 1982525SN/A iregs->regs.readReg(i), 1992525SN/A ((i == j) ? "\n" : " ")); 2001904SN/A outs << "\n"; 2011904SN/A } 2021904SN/A 2031904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2041904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2051904SN/A 2061904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2071904SN/A outs << " CPSeq=" << dec << cp_seq; 2081967SN/A 2091967SN/A // 2101967SN/A // End of line... 2111967SN/A // 2121967SN/A outs << endl; 2132SN/A } 2142SN/A} 2152SN/A 2162SN/A 2172SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 2181967SN/Astring Trace::InstRecord::trace_system; 2192SN/A 2202SN/A//////////////////////////////////////////////////////////////////////// 2212SN/A// 2222SN/A// Parameter space for per-cycle execution address tracing options. 2232SN/A// Derive from ParamContext so we can override checkParams() function. 2242SN/A// 2252SN/Aclass ExecutionTraceParamContext : public ParamContext 2262SN/A{ 2272SN/A public: 2282SN/A ExecutionTraceParamContext(const string &_iniSection) 2292SN/A : ParamContext(_iniSection) 2302SN/A { 2312SN/A } 2322SN/A 2332SN/A void checkParams(); // defined at bottom of file 2342SN/A}; 2352SN/A 2362SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 2372SN/A 2382SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 2391413SN/A "capture speculative instructions", true); 2402SN/A 2412SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 2422SN/A "print cycle number", true); 2432SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 2442SN/A "print op class", true); 2452SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 2462SN/A "print thread number", true); 2472SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 2482SN/A "print effective address", true); 2492SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 2502SN/A "print result data", true); 2512SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 2522SN/A "print all integer regs", false); 2532SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 2542SN/A "print fetch sequence number", false); 2552SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 2562SN/A "print correct-path sequence number", false); 2572973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 2582973Sgblack@eecs.umich.edu "print which registers changed to what", false); 2592299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 2602299SN/A "Use symbols for the PC if available", true); 2611904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 2621904SN/A "print trace in intel compatible format", false); 2631967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 2641967SN/A "print trace of which system (client or server)", 2651967SN/A "client"); 2661904SN/A 2672SN/A 2682SN/A// 2692SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 2702SN/A// to get us into the InstRecord namespace 2712SN/A// 2722SN/Avoid 2732SN/ATrace::InstRecord::setParams() 2742SN/A{ 2752SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 2762SN/A 2772SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 2782SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 2792SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 2802SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 2812SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 2822SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 2832SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 2842SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 2852973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 2862299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 2871904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 2881967SN/A trace_system = exe_trace_system; 2892SN/A} 2902SN/A 2912SN/Avoid 2922SN/AExecutionTraceParamContext::checkParams() 2932SN/A{ 2942SN/A Trace::InstRecord::setParams(); 2952SN/A} 2962SN/A 297