exetrace.cc revision 3059
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 362SN/A 372973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 3856SN/A#include "base/loader/symtab.hh" 391717SN/A#include "cpu/base.hh" 402518SN/A#include "cpu/exetrace.hh" 4156SN/A#include "cpu/static_inst.hh" 422518SN/A#include "sim/param.hh" 432518SN/A#include "sim/system.hh" 442SN/A 452SN/Ausing namespace std; 462973Sgblack@eecs.umich.eduusing namespace TheISA; 472SN/A 482SN/A//////////////////////////////////////////////////////////////////////// 492SN/A// 502SN/A// Methods for the InstRecord object 512SN/A// 522SN/A 532SN/A 542SN/Avoid 552SN/ATrace::InstRecord::dump(ostream &outs) 562SN/A{ 573059Sgblack@eecs.umich.edu static uint64_t regs[32] = { 583059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 593059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 603059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 613059Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 623059Sgblack@eecs.umich.edu static uint64_t ccr = 0; 633059Sgblack@eecs.umich.edu static uint64_t y = 0; 643059Sgblack@eecs.umich.edu static uint64_t floats[32]; 653059Sgblack@eecs.umich.edu uint64_t newVal; 663059Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 672973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 682973Sgblack@eecs.umich.edu { 693059Sgblack@eecs.umich.edu ThreadContext * context = cpu->threadContexts[0]; 703059Sgblack@eecs.umich.edu char buf[256]; 713059Sgblack@eecs.umich.edu sprintf(buf, "PC = 0x%016llx", context->readNextPC()); 723059Sgblack@eecs.umich.edu outs << buf; 733059Sgblack@eecs.umich.edu sprintf(buf, " NPC = 0x%016llx", context->readNextNPC()); 743059Sgblack@eecs.umich.edu outs << buf; 753059Sgblack@eecs.umich.edu newVal = context->readMiscReg(SparcISA::MISCREG_CCR); 763059Sgblack@eecs.umich.edu if(newVal != ccr) 773059Sgblack@eecs.umich.edu { 783059Sgblack@eecs.umich.edu sprintf(buf, " CCR = 0x%016llx", newVal); 793059Sgblack@eecs.umich.edu outs << buf; 803059Sgblack@eecs.umich.edu ccr = newVal; 813059Sgblack@eecs.umich.edu } 823059Sgblack@eecs.umich.edu newVal = context->readMiscReg(SparcISA::MISCREG_Y); 833059Sgblack@eecs.umich.edu if(newVal != y) 843059Sgblack@eecs.umich.edu { 853059Sgblack@eecs.umich.edu sprintf(buf, " Y = 0x%016llx", newVal); 863059Sgblack@eecs.umich.edu outs << buf; 873059Sgblack@eecs.umich.edu y = newVal; 883059Sgblack@eecs.umich.edu } 893059Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 903059Sgblack@eecs.umich.edu { 913059Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 923059Sgblack@eecs.umich.edu { 933059Sgblack@eecs.umich.edu int index = x + 8 * y; 943059Sgblack@eecs.umich.edu newVal = context->readIntReg(index); 953059Sgblack@eecs.umich.edu if(regs[index] != newVal) 963059Sgblack@eecs.umich.edu { 973059Sgblack@eecs.umich.edu sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal); 983059Sgblack@eecs.umich.edu outs << buf; 993059Sgblack@eecs.umich.edu regs[index] = newVal; 1003059Sgblack@eecs.umich.edu } 1013059Sgblack@eecs.umich.edu } 1023059Sgblack@eecs.umich.edu } 1033059Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1043059Sgblack@eecs.umich.edu { 1053059Sgblack@eecs.umich.edu newVal = context->readFloatRegBits(2 * y, 64); 1063059Sgblack@eecs.umich.edu if(floats[y] != newVal) 1073059Sgblack@eecs.umich.edu { 1083059Sgblack@eecs.umich.edu sprintf(buf, " F%d = 0x%016llx", y, newVal); 1093059Sgblack@eecs.umich.edu outs << buf; 1103059Sgblack@eecs.umich.edu floats[y] = newVal; 1113059Sgblack@eecs.umich.edu } 1123059Sgblack@eecs.umich.edu } 1133059Sgblack@eecs.umich.edu outs << endl; 1142973Sgblack@eecs.umich.edu /* 1152973Sgblack@eecs.umich.edu int numSources = staticInst->numSrcRegs(); 1162973Sgblack@eecs.umich.edu int numDests = staticInst->numDestRegs(); 1172973Sgblack@eecs.umich.edu outs << "Sources:"; 1182973Sgblack@eecs.umich.edu for(int x = 0; x < numSources; x++) 1192973Sgblack@eecs.umich.edu { 1202973Sgblack@eecs.umich.edu int sourceNum = staticInst->srcRegIdx(x); 1212973Sgblack@eecs.umich.edu if(sourceNum < FP_Base_DepTag) 1222973Sgblack@eecs.umich.edu outs << " " << getIntRegName(sourceNum); 1232973Sgblack@eecs.umich.edu else if(sourceNum < Ctrl_Base_DepTag) 1242973Sgblack@eecs.umich.edu outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag); 1252973Sgblack@eecs.umich.edu else 1262973Sgblack@eecs.umich.edu outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag); 1272973Sgblack@eecs.umich.edu } 1282973Sgblack@eecs.umich.edu outs << endl; 1292973Sgblack@eecs.umich.edu outs << "Destinations:"; 1302973Sgblack@eecs.umich.edu for(int x = 0; x < numDests; x++) 1312973Sgblack@eecs.umich.edu { 1322973Sgblack@eecs.umich.edu int destNum = staticInst->destRegIdx(x); 1332973Sgblack@eecs.umich.edu if(destNum < FP_Base_DepTag) 1342973Sgblack@eecs.umich.edu outs << " " << getIntRegName(destNum); 1352973Sgblack@eecs.umich.edu else if(destNum < Ctrl_Base_DepTag) 1362973Sgblack@eecs.umich.edu outs << " " << getFloatRegName(destNum - FP_Base_DepTag); 1372973Sgblack@eecs.umich.edu else 1382973Sgblack@eecs.umich.edu outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag); 1392973Sgblack@eecs.umich.edu } 1402973Sgblack@eecs.umich.edu outs << endl;*/ 1412973Sgblack@eecs.umich.edu } 1422973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1431968SN/A#if FULL_SYSTEM 1441968SN/A bool is_trace_system = (cpu->system->name() == trace_system); 1451968SN/A#else 1461968SN/A bool is_trace_system = true; 1471968SN/A#endif 1481968SN/A if (is_trace_system) { 1491967SN/A ccprintf(outs, "%7d ) ", cycle); 1501967SN/A outs << "0x" << hex << PC << ":\t"; 1511967SN/A if (staticInst->isLoad()) { 1521967SN/A outs << "<RD 0x" << hex << addr; 1531967SN/A outs << ">"; 1541967SN/A } else if (staticInst->isStore()) { 1551967SN/A outs << "<WR 0x" << hex << addr; 1561967SN/A outs << ">"; 1571967SN/A } 1581967SN/A outs << endl; 1591904SN/A } 1601904SN/A } else { 1611904SN/A if (flags[PRINT_CYCLE]) 1621904SN/A ccprintf(outs, "%7d: ", cycle); 163452SN/A 1641904SN/A outs << cpu->name() << " "; 1652SN/A 1661904SN/A if (flags[TRACE_MISSPEC]) 1671904SN/A outs << (misspeculating ? "-" : "+") << " "; 1682SN/A 1691904SN/A if (flags[PRINT_THREAD_NUM]) 1701904SN/A outs << "T" << thread << " : "; 1712SN/A 1722SN/A 1731904SN/A std::string sym_str; 1741904SN/A Addr sym_addr; 1751904SN/A if (debugSymbolTable 1762299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1772299SN/A && flags[PC_SYMBOL]) { 1781904SN/A if (PC != sym_addr) 1791904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1801904SN/A outs << "@" << sym_str << " : "; 1811904SN/A } 1821904SN/A else { 1831904SN/A outs << "0x" << hex << PC << " : "; 1841904SN/A } 185452SN/A 1861904SN/A // 1871904SN/A // Print decoded instruction 1881904SN/A // 1892SN/A 1902SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1911904SN/A // There's a bug in gcc 2.x library that prevents setw() 1921904SN/A // from working properly on strings 1931904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1941904SN/A while (mc.length() < 26) 1951904SN/A mc += " "; 1961904SN/A outs << mc; 1972SN/A#else 1981904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1992SN/A#endif 2002SN/A 2011904SN/A outs << " : "; 2022SN/A 2031904SN/A if (flags[PRINT_OP_CLASS]) { 2041904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2051904SN/A } 2061904SN/A 2071904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2081904SN/A outs << " D="; 2091904SN/A#if 0 2101904SN/A if (data_status == DataDouble) 2111904SN/A ccprintf(outs, "%f", data.as_double); 2121904SN/A else 2131904SN/A ccprintf(outs, "%#018x", data.as_int); 2141904SN/A#else 2151904SN/A ccprintf(outs, "%#018x", data.as_int); 2161904SN/A#endif 2171904SN/A } 2181904SN/A 2191904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2201904SN/A outs << " A=0x" << hex << addr; 2211904SN/A 2221904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2232525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2241904SN/A for (int j = i + 1; i <= j; i++) 2252525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2262525SN/A iregs->regs.readReg(i), 2272525SN/A ((i == j) ? "\n" : " ")); 2281904SN/A outs << "\n"; 2291904SN/A } 2301904SN/A 2311904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2321904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2331904SN/A 2341904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2351904SN/A outs << " CPSeq=" << dec << cp_seq; 2361967SN/A 2371967SN/A // 2381967SN/A // End of line... 2391967SN/A // 2401967SN/A outs << endl; 2412SN/A } 2422SN/A} 2432SN/A 2442SN/A 2452SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 2461967SN/Astring Trace::InstRecord::trace_system; 2472SN/A 2482SN/A//////////////////////////////////////////////////////////////////////// 2492SN/A// 2502SN/A// Parameter space for per-cycle execution address tracing options. 2512SN/A// Derive from ParamContext so we can override checkParams() function. 2522SN/A// 2532SN/Aclass ExecutionTraceParamContext : public ParamContext 2542SN/A{ 2552SN/A public: 2562SN/A ExecutionTraceParamContext(const string &_iniSection) 2572SN/A : ParamContext(_iniSection) 2582SN/A { 2592SN/A } 2602SN/A 2612SN/A void checkParams(); // defined at bottom of file 2622SN/A}; 2632SN/A 2642SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 2652SN/A 2662SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 2671413SN/A "capture speculative instructions", true); 2682SN/A 2692SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 2702SN/A "print cycle number", true); 2712SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 2722SN/A "print op class", true); 2732SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 2742SN/A "print thread number", true); 2752SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 2762SN/A "print effective address", true); 2772SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 2782SN/A "print result data", true); 2792SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 2802SN/A "print all integer regs", false); 2812SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 2822SN/A "print fetch sequence number", false); 2832SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 2842SN/A "print correct-path sequence number", false); 2852973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 2862973Sgblack@eecs.umich.edu "print which registers changed to what", false); 2872299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 2882299SN/A "Use symbols for the PC if available", true); 2891904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 2901904SN/A "print trace in intel compatible format", false); 2911967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 2921967SN/A "print trace of which system (client or server)", 2931967SN/A "client"); 2941904SN/A 2952SN/A 2962SN/A// 2972SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 2982SN/A// to get us into the InstRecord namespace 2992SN/A// 3002SN/Avoid 3012SN/ATrace::InstRecord::setParams() 3022SN/A{ 3032SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 3042SN/A 3052SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 3062SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 3072SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 3082SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 3092SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 3102SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 3112SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 3122SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 3132973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 3142299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 3151904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 3161967SN/A trace_system = exe_trace_system; 3172SN/A} 3182SN/A 3192SN/Avoid 3202SN/AExecutionTraceParamContext::checkParams() 3212SN/A{ 3222SN/A Trace::InstRecord::setParams(); 3232SN/A} 3242SN/A 325