exec_context.hh revision 8779
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A#error "Cannot include this file" 321388SN/A 332SN/A/** 342SN/A * The ExecContext is not a usable class. It is simply here for 352SN/A * documentation purposes. It shows the interface that is used by the 361191SN/A * ISA to access and change CPU state. 371191SN/A */ 381191SN/Aclass ExecContext { 391388SN/A // The register accessor methods provide the index of the 401717SN/A // instruction's operand (e.g., 0 or 1), not the architectural 412651Ssaidi@eecs.umich.edu // register index, to simplify the implementation of register 422680Sktlim@umich.edu // renaming. We find the architectural register index by indexing 431977SN/A // into the instruction's own operand index table. Note that a 443144Shsul@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 45161SN/A // ref-counted StaticInstPtr to reduce overhead. This is fine as 462190SN/A // long as these methods don't copy the pointer into any long-term 4756SN/A // storage (which is pretty hard to imagine they would have reason 482190SN/A // to do). 492SN/A 501062SN/A /** Reads an integer register. */ 511062SN/A uint64_t readIntRegOperand(const StaticInst *si, int idx); 522359SN/A 532359SN/A /** Reads a floating point register of single register width. */ 542359SN/A FloatReg readFloatRegOperand(const StaticInst *si, int idx); 552SN/A 562SN/A /** Reads a floating point register in its binary format, instead 572SN/A * of by value. */ 582SN/A FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 592SN/A 602SN/A /** Sets an integer register to a value. */ 612SN/A void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 622SN/A 632SN/A /** Sets a floating point register of single width to a value. */ 643126Sktlim@umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 653126Sktlim@umich.edu 664075Sbinkertn@umich.edu /** Sets the bits of a floating point register of single width 673126Sktlim@umich.edu * to a binary value. */ 683126Sktlim@umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 693126Sktlim@umich.edu FloatRegBits val); 703126Sktlim@umich.edu 713126Sktlim@umich.edu /** Reads the PC. */ 723126Sktlim@umich.edu uint64_t readPC(); 732356SN/A /** Reads the NextPC. */ 742356SN/A uint64_t readNextPC(); 752356SN/A /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 762367SN/A uint64_t readNextNPC(); 772356SN/A 782356SN/A /** Sets the PC. */ 792367SN/A void setPC(uint64_t val); 802356SN/A /** Sets the NextPC. */ 812356SN/A void setNextPC(uint64_t val); 822356SN/A /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 832367SN/A void setNextNPC(uint64_t val); 842367SN/A 852367SN/A /** Reads a miscellaneous register. */ 862367SN/A MiscReg readMiscRegNoEffect(int misc_reg); 872356SN/A 882356SN/A /** Reads a miscellaneous register, handling any architectural 892356SN/A * side effects due to reading that register. */ 902356SN/A MiscReg readMiscReg(int misc_reg); 912356SN/A 922356SN/A /** Sets a miscellaneous register. */ 932356SN/A void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 942356SN/A 952356SN/A /** Sets a miscellaneous register, handling any architectural 962356SN/A * side effects due to writing that register. */ 971858SN/A void setMiscReg(int misc_reg, const MiscReg &val); 981400SN/A 993923Shsul@eecs.umich.edu /** Records the effective address of the instruction. Only valid 1003661Srdreslin@umich.edu * for memory ops. */ 1013661Srdreslin@umich.edu void setEA(Addr EA); 1022SN/A /** Returns the effective address of the instruction. Only valid 1031400SN/A * for memory ops. */ 1042856Srdreslin@umich.edu Addr getEA(); 1053661Srdreslin@umich.edu 1063661Srdreslin@umich.edu /** Returns a pointer to the ThreadContext. */ 1072SN/A ThreadContext *tcBase(); 1082SN/A 1092359SN/A Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1102831Sksewell@umich.edu 1111062SN/A Fault writeMem(uint8_t *data, unsigned size, 1122SN/A Addr addr, unsigned flags, uint64_t *res); 1132SN/A 1142SN/A /** Somewhat Alpha-specific function that handles returning from 1152831Sksewell@umich.edu * an error or interrupt. */ 1161062SN/A Fault hwrei(); 1171062SN/A 1182SN/A /** 1192SN/A * Check for special simulator handling of specific PAL calls. If 1202SN/A * return value is false, actual PAL call will be suppressed. 1212SN/A */ 1221354SN/A bool simPalCheck(int palFunc); 1232SN/A 124503SN/A /** Executes a syscall specified by the callnum. */ 1252SN/A void syscall(int64_t callnum); 1262SN/A 1272SN/A /** Finish a DTB address translation. */ 1282SN/A void finishTranslation(WholeTranslationState *state); 1291400SN/A}; 1302SN/A