exec_context.hh revision 7725:00ea9430643b 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#error "Cannot include this file"
32
33/**
34 * The ExecContext is not a usable class.  It is simply here for
35 * documentation purposes.  It shows the interface that is used by the
36 * ISA to access and change CPU state.
37 */
38class ExecContext {
39    // The register accessor methods provide the index of the
40    // instruction's operand (e.g., 0 or 1), not the architectural
41    // register index, to simplify the implementation of register
42    // renaming.  We find the architectural register index by indexing
43    // into the instruction's own operand index table.  Note that a
44    // raw pointer to the StaticInst is provided instead of a
45    // ref-counted StaticInstPtr to reduce overhead.  This is fine as
46    // long as these methods don't copy the pointer into any long-term
47    // storage (which is pretty hard to imagine they would have reason
48    // to do).
49
50    /** Reads an integer register. */
51    uint64_t readIntRegOperand(const StaticInst *si, int idx);
52
53    /** Reads a floating point register of single register width. */
54    FloatReg readFloatRegOperand(const StaticInst *si, int idx);
55
56    /** Reads a floating point register in its binary format, instead
57     * of by value. */
58    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
59
60    /** Sets an integer register to a value. */
61    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
62
63    /** Sets a floating point register of single width to a value. */
64    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
65
66    /** Sets the bits of a floating point register of single width
67     * to a binary value. */
68    void setFloatRegOperandBits(const StaticInst *si, int idx,
69                                FloatRegBits val);
70
71    /** Reads the PC. */
72    uint64_t readPC();
73    /** Reads the NextPC. */
74    uint64_t readNextPC();
75    /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */
76    uint64_t readNextNPC();
77
78    /** Sets the PC. */
79    void setPC(uint64_t val);
80    /** Sets the NextPC. */
81    void setNextPC(uint64_t val);
82    /** Sets the Next-NextPC.  Only for architectures like SPARC or MIPS. */
83    void setNextNPC(uint64_t val);
84
85    /** Reads a miscellaneous register. */
86    MiscReg readMiscRegNoEffect(int misc_reg);
87
88    /** Reads a miscellaneous register, handling any architectural
89     * side effects due to reading that register. */
90    MiscReg readMiscReg(int misc_reg);
91
92    /** Sets a miscellaneous register. */
93    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
94
95    /** Sets a miscellaneous register, handling any architectural
96     * side effects due to writing that register. */
97    void setMiscReg(int misc_reg, const MiscReg &val);
98
99    /** Records the effective address of the instruction.  Only valid
100     * for memory ops. */
101    void setEA(Addr EA);
102    /** Returns the effective address of the instruction.  Only valid
103     * for memory ops. */
104    Addr getEA();
105
106    /** Returns a pointer to the ThreadContext. */
107    ThreadContext *tcBase();
108
109    /** Reads an address, creating a memory request with the given
110     * flags.  Stores result of read in data. */
111    template <class T>
112    Fault read(Addr addr, T &data, unsigned flags);
113
114    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
115
116    /** Writes to an address, creating a memory request with the given
117     * flags.  Writes data to memory.  For store conditionals, returns
118     * the result of the store in res. */
119    template <class T>
120    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
121
122    Fault writeBytes(uint8_t *data, unsigned size,
123                     Addr addr, unsigned flags, uint64_t *res);
124
125#if FULL_SYSTEM
126    /** Somewhat Alpha-specific function that handles returning from
127     * an error or interrupt. */
128    Fault hwrei();
129
130    /**
131     * Check for special simulator handling of specific PAL calls.  If
132     * return value is false, actual PAL call will be suppressed.
133     */
134    bool simPalCheck(int palFunc);
135#else
136    /** Executes a syscall specified by the callnum. */
137    void syscall(int64_t callnum);
138#endif
139
140    /** Finish a DTB address translation. */
141    void finishTranslation(WholeTranslationState *state);
142};
143