exec_context.hh revision 6314:781969fbeca9
13115SN/A/* 24125SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 33115SN/A * All rights reserved. 43115SN/A * 53115SN/A * Redistribution and use in source and binary forms, with or without 63115SN/A * modification, are permitted provided that the following conditions are 73115SN/A * met: redistributions of source code must retain the above copyright 83115SN/A * notice, this list of conditions and the following disclaimer; 93115SN/A * redistributions in binary form must reproduce the above copyright 103115SN/A * notice, this list of conditions and the following disclaimer in the 113115SN/A * documentation and/or other materials provided with the distribution; 123115SN/A * neither the name of the copyright holders nor the names of its 133115SN/A * contributors may be used to endorse or promote products derived from 143115SN/A * this software without specific prior written permission. 153115SN/A * 163115SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173115SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183115SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193115SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203115SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213115SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223115SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233115SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243115SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253115SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263115SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273115SN/A * 283115SN/A * Authors: Kevin Lim 293115SN/A */ 303115SN/A 316406SN/A#error "Cannot include this file" 326406SN/A 336406SN/A/** 343115SN/A * The ExecContext is not a usable class. It is simply here for 353115SN/A * documentation purposes. It shows the interface that is used by the 368229Snate@binkert.org * ISA to access and change CPU state. 373115SN/A */ 383115SN/Aclass ExecContext { 398229Snate@binkert.org // The register accessor methods provide the index of the 408229Snate@binkert.org // instruction's operand (e.g., 0 or 1), not the architectural 418229Snate@binkert.org // register index, to simplify the implementation of register 428229Snate@binkert.org // renaming. We find the architectural register index by indexing 438229Snate@binkert.org // into the instruction's own operand index table. Note that a 448229Snate@binkert.org // raw pointer to the StaticInst is provided instead of a 458229Snate@binkert.org // ref-counted StaticInstPtr to reduce overhead. This is fine as 468229Snate@binkert.org // long as these methods don't copy the pointer into any long-term 473115SN/A // storage (which is pretty hard to imagine they would have reason 483115SN/A // to do). 493115SN/A 503115SN/A /** Reads an integer register. */ 518108SN/A uint64_t readIntRegOperand(const StaticInst *si, int idx); 528108SN/A 533115SN/A /** Reads a floating point register of single register width. */ 547414SN/A FloatReg readFloatRegOperand(const StaticInst *si, int idx); 557414SN/A 567414SN/A /** Reads a floating point register in its binary format, instead 577414SN/A * of by value. */ 587414SN/A FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 598114Sgblack@eecs.umich.edu 603115SN/A /** Sets an integer register to a value. */ 613115SN/A void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 628108SN/A 638108SN/A /** Sets a floating point register of single width to a value. */ 643115SN/A void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 654779SN/A 664779SN/A /** Sets the bits of a floating point register of single width 674779SN/A * to a binary value. */ 683115SN/A void setFloatRegOperandBits(const StaticInst *si, int idx, 694779SN/A FloatRegBits val); 704779SN/A 714779SN/A /** Reads the PC. */ 726408SN/A uint64_t readPC(); 737414SN/A /** Reads the NextPC. */ 747414SN/A uint64_t readNextPC(); 757414SN/A /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 767414SN/A uint64_t readNextNPC(); 777414SN/A 788108SN/A /** Sets the PC. */ 798108SN/A void setPC(uint64_t val); 804779SN/A /** Sets the NextPC. */ 814779SN/A void setNextPC(uint64_t val); 823115SN/A /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 838108SN/A void setNextNPC(uint64_t val); 846408SN/A 858108SN/A /** Reads a miscellaneous register. */ 866408SN/A MiscReg readMiscRegNoEffect(int misc_reg); 876408SN/A 886408SN/A /** Reads a miscellaneous register, handling any architectural 896408SN/A * side effects due to reading that register. */ 906408SN/A MiscReg readMiscReg(int misc_reg); 918108SN/A 924779SN/A /** Sets a miscellaneous register. */ 938108SN/A void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 944779SN/A 958108SN/A /** Sets a miscellaneous register, handling any architectural 964779SN/A * side effects due to writing that register. */ 978108SN/A void setMiscReg(int misc_reg, const MiscReg &val); 984779SN/A 994779SN/A /** Records the effective address of the instruction. Only valid 1004245SN/A * for memory ops. */ 1013115SN/A void setEA(Addr EA); 1024779SN/A /** Returns the effective address of the instruction. Only valid 1034779SN/A * for memory ops. */ 1048108SN/A Addr getEA(); 1054779SN/A 1064779SN/A /** Returns a pointer to the ThreadContext. */ 1074779SN/A ThreadContext *tcBase(); 1083115SN/A 1094779SN/A /** Reads an address, creating a memory request with the given 1108108SN/A * flags. Stores result of read in data. */ 1118108SN/A template <class T> 1124779SN/A Fault read(Addr addr, T &data, unsigned flags); 1134779SN/A 1144779SN/A /** Writes to an address, creating a memory request with the given 1156422SN/A * flags. Writes data to memory. For store conditionals, returns 1168108SN/A * the result of the store in res. */ 1174779SN/A template <class T> 1188108SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1194779SN/A 1204779SN/A /** Prefetches an address, creating a memory request with the 1214779SN/A * given flags. */ 1224779SN/A void prefetch(Addr addr, unsigned flags); 1238108SN/A 1244779SN/A /** Hints to the memory system that an address will be written to 1254779SN/A * soon, with the given size. Creates a memory request with the 1264779SN/A * given flags. */ 1274779SN/A void writeHint(Addr addr, int size, unsigned flags); 1286408SN/A 1298108SN/A#if FULL_SYSTEM 1304779SN/A /** Somewhat Alpha-specific function that handles returning from 1314779SN/A * an error or interrupt. */ 1324779SN/A Fault hwrei(); 1334779SN/A 1344779SN/A /** 1354779SN/A * Check for special simulator handling of specific PAL calls. If 1364779SN/A * return value is false, actual PAL call will be suppressed. 1374779SN/A */ 1384779SN/A bool simPalCheck(int palFunc); 1394779SN/A#else 1408108SN/A /** Executes a syscall specified by the callnum. */ 1414779SN/A void syscall(int64_t callnum); 1424779SN/A#endif 1434779SN/A}; 1448108SN/A