exec_context.hh revision 2670:9107b8bd08cd
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_EXEC_CONTEXT_HH__ 32#define __CPU_EXEC_CONTEXT_HH__ 33 34#include "config/full_system.hh" 35#include "mem/request.hh" 36#include "sim/faults.hh" 37#include "sim/host.hh" 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; 46class EndQuiesceEvent; 47class Event; 48class TranslatingPort; 49class FunctionalPort; 50class VirtualPort; 51class Process; 52class System; 53namespace Kernel { 54 class Statistics; 55}; 56 57class ExecContext 58{ 59 protected: 60 typedef TheISA::RegFile RegFile; 61 typedef TheISA::MachInst MachInst; 62 typedef TheISA::IntReg IntReg; 63 typedef TheISA::FloatReg FloatReg; 64 typedef TheISA::FloatRegBits FloatRegBits; 65 typedef TheISA::MiscRegFile MiscRegFile; 66 typedef TheISA::MiscReg MiscReg; 67 public: 68 enum Status 69 { 70 /// Initialized but not running yet. All CPUs start in 71 /// this state, but most transition to Active on cycle 1. 72 /// In MP or SMT systems, non-primary contexts will stay 73 /// in this state until a thread is assigned to them. 74 Unallocated, 75 76 /// Running. Instructions should be executed only when 77 /// the context is in this state. 78 Active, 79 80 /// Temporarily inactive. Entered while waiting for 81 /// synchronization, etc. 82 Suspended, 83 84 /// Permanently shut down. Entered when target executes 85 /// m5exit pseudo-instruction. When all contexts enter 86 /// this state, the simulation will terminate. 87 Halted 88 }; 89 90 virtual ~ExecContext() { }; 91 92 virtual BaseCPU *getCpuPtr() = 0; 93 94 virtual void setCpuId(int id) = 0; 95 96 virtual int readCpuId() = 0; 97 98#if FULL_SYSTEM 99 virtual System *getSystemPtr() = 0; 100 101 virtual AlphaITB *getITBPtr() = 0; 102 103 virtual AlphaDTB * getDTBPtr() = 0; 104 105 virtual Kernel::Statistics *getKernelStats() = 0; 106 107 virtual FunctionalPort *getPhysPort() = 0; 108 109 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 110 111 virtual void delVirtPort(VirtualPort *vp) = 0; 112#else 113 virtual TranslatingPort *getMemPort() = 0; 114 115 virtual Process *getProcessPtr() = 0; 116#endif 117 118 virtual Status status() const = 0; 119 120 virtual void setStatus(Status new_status) = 0; 121 122 /// Set the status to Active. Optional delay indicates number of 123 /// cycles to wait before beginning execution. 124 virtual void activate(int delay = 1) = 0; 125 126 /// Set the status to Suspended. 127 virtual void suspend() = 0; 128 129 /// Set the status to Unallocated. 130 virtual void deallocate() = 0; 131 132 /// Set the status to Halted. 133 virtual void halt() = 0; 134 135#if FULL_SYSTEM 136 virtual void dumpFuncProfile() = 0; 137#endif 138 139 virtual void takeOverFrom(ExecContext *old_context) = 0; 140 141 virtual void regStats(const std::string &name) = 0; 142 143 virtual void serialize(std::ostream &os) = 0; 144 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 145 146#if FULL_SYSTEM 147 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 148 149 // Not necessarily the best location for these... 150 // Having an extra function just to read these is obnoxious 151 virtual Tick readLastActivate() = 0; 152 virtual Tick readLastSuspend() = 0; 153 154 virtual void profileClear() = 0; 155 virtual void profileSample() = 0; 156#endif 157 158 virtual int getThreadNum() = 0; 159 160 // Also somewhat obnoxious. Really only used for the TLB fault. 161 // However, may be quite useful in SPARC. 162 virtual TheISA::MachInst getInst() = 0; 163 164 virtual void copyArchRegs(ExecContext *xc) = 0; 165 166 virtual void clearArchRegs() = 0; 167 168 // 169 // New accessors for new decoder. 170 // 171 virtual uint64_t readIntReg(int reg_idx) = 0; 172 173 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 174 175 virtual FloatReg readFloatReg(int reg_idx) = 0; 176 177 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 178 179 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 180 181 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 182 183 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 184 185 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 186 187 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 188 189 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 190 191 virtual uint64_t readPC() = 0; 192 193 virtual void setPC(uint64_t val) = 0; 194 195 virtual uint64_t readNextPC() = 0; 196 197 virtual void setNextPC(uint64_t val) = 0; 198 199 virtual uint64_t readNextNPC() = 0; 200 201 virtual void setNextNPC(uint64_t val) = 0; 202 203 virtual MiscReg readMiscReg(int misc_reg) = 0; 204 205 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 206 207 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 208 209 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 210 211 // Also not necessarily the best location for these two. Hopefully will go 212 // away once we decide upon where st cond failures goes. 213 virtual unsigned readStCondFailures() = 0; 214 215 virtual void setStCondFailures(unsigned sc_failures) = 0; 216 217#if FULL_SYSTEM 218 virtual bool inPalMode() = 0; 219#endif 220 221 // Only really makes sense for old CPU model. Still could be useful though. 222 virtual bool misspeculating() = 0; 223 224#if !FULL_SYSTEM 225 virtual IntReg getSyscallArg(int i) = 0; 226 227 // used to shift args for indirect syscall 228 virtual void setSyscallArg(int i, IntReg val) = 0; 229 230 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 231 232 233 // Same with st cond failures. 234 virtual Counter readFuncExeInst() = 0; 235#endif 236 237 virtual void changeRegFileContext(RegFile::ContextParam param, 238 RegFile::ContextVal val) = 0; 239}; 240 241template <class XC> 242class ProxyExecContext : public ExecContext 243{ 244 public: 245 ProxyExecContext(XC *actual_xc) 246 { actualXC = actual_xc; } 247 248 private: 249 XC *actualXC; 250 251 public: 252 253 BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } 254 255 void setCpuId(int id) { actualXC->setCpuId(id); } 256 257 int readCpuId() { return actualXC->readCpuId(); } 258 259#if FULL_SYSTEM 260 System *getSystemPtr() { return actualXC->getSystemPtr(); } 261 262 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 263 264 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 265 266 Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } 267 268 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 269 270 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 271 272 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 273#else 274 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 275 276 Process *getProcessPtr() { return actualXC->getProcessPtr(); } 277#endif 278 279 Status status() const { return actualXC->status(); } 280 281 void setStatus(Status new_status) { actualXC->setStatus(new_status); } 282 283 /// Set the status to Active. Optional delay indicates number of 284 /// cycles to wait before beginning execution. 285 void activate(int delay = 1) { actualXC->activate(delay); } 286 287 /// Set the status to Suspended. 288 void suspend() { actualXC->suspend(); } 289 290 /// Set the status to Unallocated. 291 void deallocate() { actualXC->deallocate(); } 292 293 /// Set the status to Halted. 294 void halt() { actualXC->halt(); } 295 296#if FULL_SYSTEM 297 void dumpFuncProfile() { actualXC->dumpFuncProfile(); } 298#endif 299 300 void takeOverFrom(ExecContext *oldContext) 301 { actualXC->takeOverFrom(oldContext); } 302 303 void regStats(const std::string &name) { actualXC->regStats(name); } 304 305 void serialize(std::ostream &os) { actualXC->serialize(os); } 306 void unserialize(Checkpoint *cp, const std::string §ion) 307 { actualXC->unserialize(cp, section); } 308 309#if FULL_SYSTEM 310 EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } 311 312 Tick readLastActivate() { return actualXC->readLastActivate(); } 313 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 314 315 void profileClear() { return actualXC->profileClear(); } 316 void profileSample() { return actualXC->profileSample(); } 317#endif 318 319 int getThreadNum() { return actualXC->getThreadNum(); } 320 321 // @todo: Do I need this? 322 MachInst getInst() { return actualXC->getInst(); } 323 324 // @todo: Do I need this? 325 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 326 327 void clearArchRegs() { actualXC->clearArchRegs(); } 328 329 // 330 // New accessors for new decoder. 331 // 332 uint64_t readIntReg(int reg_idx) 333 { return actualXC->readIntReg(reg_idx); } 334 335 FloatReg readFloatReg(int reg_idx, int width) 336 { return actualXC->readFloatReg(reg_idx, width); } 337 338 FloatReg readFloatReg(int reg_idx) 339 { return actualXC->readFloatReg(reg_idx); } 340 341 FloatRegBits readFloatRegBits(int reg_idx, int width) 342 { return actualXC->readFloatRegBits(reg_idx, width); } 343 344 FloatRegBits readFloatRegBits(int reg_idx) 345 { return actualXC->readFloatRegBits(reg_idx); } 346 347 void setIntReg(int reg_idx, uint64_t val) 348 { actualXC->setIntReg(reg_idx, val); } 349 350 void setFloatReg(int reg_idx, FloatReg val, int width) 351 { actualXC->setFloatReg(reg_idx, val, width); } 352 353 void setFloatReg(int reg_idx, FloatReg val) 354 { actualXC->setFloatReg(reg_idx, val); } 355 356 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 357 { actualXC->setFloatRegBits(reg_idx, val, width); } 358 359 void setFloatRegBits(int reg_idx, FloatRegBits val) 360 { actualXC->setFloatRegBits(reg_idx, val); } 361 362 uint64_t readPC() { return actualXC->readPC(); } 363 364 void setPC(uint64_t val) { actualXC->setPC(val); } 365 366 uint64_t readNextPC() { return actualXC->readNextPC(); } 367 368 void setNextPC(uint64_t val) { actualXC->setNextPC(val); } 369 370 uint64_t readNextNPC() { return actualXC->readNextNPC(); } 371 372 void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); } 373 374 MiscReg readMiscReg(int misc_reg) 375 { return actualXC->readMiscReg(misc_reg); } 376 377 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 378 { return actualXC->readMiscRegWithEffect(misc_reg, fault); } 379 380 Fault setMiscReg(int misc_reg, const MiscReg &val) 381 { return actualXC->setMiscReg(misc_reg, val); } 382 383 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 384 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 385 386 unsigned readStCondFailures() 387 { return actualXC->readStCondFailures(); } 388 389 void setStCondFailures(unsigned sc_failures) 390 { actualXC->setStCondFailures(sc_failures); } 391#if FULL_SYSTEM 392 bool inPalMode() { return actualXC->inPalMode(); } 393#endif 394 395 // @todo: Fix this! 396 bool misspeculating() { return actualXC->misspeculating(); } 397 398#if !FULL_SYSTEM 399 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 400 401 // used to shift args for indirect syscall 402 void setSyscallArg(int i, IntReg val) 403 { actualXC->setSyscallArg(i, val); } 404 405 void setSyscallReturn(SyscallReturn return_value) 406 { actualXC->setSyscallReturn(return_value); } 407 408 409 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } 410#endif 411 412 void changeRegFileContext(RegFile::ContextParam param, 413 RegFile::ContextVal val) 414 { 415 actualXC->changeRegFileContext(param, val); 416 } 417}; 418 419#endif 420